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公开(公告)号：US20240315152A1
公开(公告)日：2024-09-19
申请号：US18669541
申请日：2024-05-21
发明人： Hung-Li Chiang , Jer-Fu Wang , Chao-Ching Cheng , Tzu-Chiang Chen
CPC分类号： H10N70/8413 , H10B63/20 , H10N70/011 , H10N70/231 , H10N70/826
摘要： A method of forming a memory device includes the following operations. A first conductive plug is formed within a first dielectric layer over a substrate. A treating process is performed to transform a portion of the first conductive plug into a buffer layer, and the buffer layer caps the remaining portion of the first conductive plug. A phase change layer and a top electrode are sequentially formed over the buffer layer. A second dielectric layer is formed to encapsulate the top electrode and the underlying phase change layer. A second conductive plug is formed within the second dielectric layer and in physical contact with the top electrode. A filamentary bottom electrode is formed within the buffer layer.
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公开(公告)号：US12062696B2
公开(公告)日：2024-08-13
申请号：US18352249
申请日：2023-07-14
CPC分类号： H01L29/1033 , H01L23/36 , H01L29/0607 , H01L29/0669 , H01L29/66477 , H01L29/78
摘要： A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a heat transfer layer disposed over a substrate, a channel material layer, a gate structure and source and drain terminals. The channel material layer has a first surface and a second surface opposite to the first surface, and the channel material layer is disposed on the heat transfer layer with the first surface in contact with the heat transfer layer. The gate structure is disposed above the channel material layer. The source and drain terminals are in contact with the channel material layer and located at two opposite sides of the gate structure.
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公开(公告)号：US20240260279A1
公开(公告)日：2024-08-01
申请号：US18610689
申请日：2024-03-20
CPC分类号： H10B63/80 , G11C13/0026 , G11C13/0028 , G11C13/003 , G11C13/004 , G11C13/0069 , H10B63/20 , H10N70/011 , G11C2013/0045 , G11C2013/0078
摘要： The present disclosure relates to an integrated chip structure. The integrated chip structure includes a plurality of memory stacks disposed over a substrate and respectively having a plurality of conductive segments stacked onto one another. One or more data storage structures are on the plurality of memory stacks, one or more selectors are over the one or more data storage structures, and an upper conductor over the one or more selectors. The plurality of memory stacks include a first memory stack, a second memory stack, and a third memory stack. The first memory stack and the third memory stack are closest memory stacks to opposing sides of the second memory stack. The first memory stack is closer to the second memory stack than the third memory stack.
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公开(公告)号：US20240250122A1
公开(公告)日：2024-07-25
申请号：US18624386
申请日：2024-04-02
IPC分类号： H01L29/06 , H01L21/308 , H01L21/8234 , H01L27/088 , H01L29/66 , H01L29/78
CPC分类号： H01L29/0649 , H01L21/308 , H01L21/823431 , H01L21/823437 , H01L21/823481 , H01L27/0886 , H01L29/66545 , H01L29/66795 , H01L29/785
摘要： The structure of a semiconductor device with isolation structures between FET devices and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a fin structure on a substrate and forming polysilicon gate structures with a first threshold voltage on first fin portions of the fin structure. The method further includes forming doped fin regions with dopants of a first type conductivity on second fin portions of the fin structure, doping at least one of the polysilicon gate structures with dopants of a second type conductivity to adjust the first threshold voltage to a greater second threshold voltage, and replacing at least two of the polysilicon gate structures adjacent to the at least one of the polysilicon gate structures with metal gate structures having a third threshold voltage less than the first and second threshold voltages
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公开(公告)号：US10672667B2
公开(公告)日：2020-06-02
申请号：US16417341
申请日：2019-05-20
发明人： Chao-Ching Cheng , Tzu-Chiang Chen , Chen-Feng Hsu , Yu-Lin Yang , Tung Ying Lee , Chih Chieh Yeh
IPC分类号： H01L29/00 , H01L21/8238 , H01L27/092 , H01L29/06 , H01L29/423 , H01L29/786 , H01L29/66 , H01L21/02 , H01L21/306 , H01L29/775 , H01L29/08 , H01L21/8234 , B82Y10/00
摘要： Nanowire devices and fin devices are formed in a first region and a second region of a substrate. To form the devices, alternating layers of a first material and a second material are formed, inner spacers are formed adjacent to the layers of the first material, and then the layers of the first material are removed to form nanowires without removing the layers of the first material within the second region. Gate structures of gate dielectrics and gate electrodes are formed within the first region and the second region in order to form the nanowire devices in the first region and the fin devices in the second region.
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公开(公告)号：US20200075756A1
公开(公告)日：2020-03-05
申请号：US16678045
申请日：2019-11-08
发明人： Chao-Ching Cheng , Chih-Hsin Ko , Hsingien Wann
IPC分类号： H01L29/78 , H01L29/49 , H01L29/06 , H01L21/308 , H01L21/28 , H01L29/20 , H01L29/04 , H01L29/66 , H01L29/51 , H01L29/45
摘要： A device with improved device performance, and method of manufacturing the same, are disclosed. An exemplary device includes a group III-V compound semiconductor substrate that includes a surface having a (110) crystallographic orientation, and a gate stack disposed over the group III-V compound semiconductor substrate. The gate stack includes a high-k dielectric layer disposed on the surface having the (110) crystallographic orientation, and a gate electrode disposed over the high-k dielectric layer.
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公开(公告)号：US10522622B2
公开(公告)日：2019-12-31
申请号：US15979123
申请日：2018-05-14
IPC分类号： H01L29/76 , H01L31/113 , H01L29/06 , H01L29/78 , H01L29/66 , H01L21/02 , H01L21/8238 , H01L27/088 , H01L27/092 , H01L29/423 , H01L21/8234
摘要： A multi-gate semiconductor structure includes a plurality of nanowires, a gate structure disposed over the plurality of nanowires, and source/drain structures at two ends of each of the plurality of nanowires. The source/drain structures include a conductor, and a bottom surface of the conductor is lower than the plurality of nanowires.
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公开(公告)号：US10297508B2
公开(公告)日：2019-05-21
申请号：US15864793
申请日：2018-01-08
发明人： Chao-Ching Cheng , Tzu-Chiang Chen , Chen-Feng Hsu , Yu-Lin Yang , Tung Ying Lee , Chih Chieh Yeh
IPC分类号： H01L21/82 , H01L21/8238 , H01L27/092 , H01L29/06 , H01L29/423 , H01L29/786 , H01L29/66 , H01L21/02 , H01L21/306
摘要： Nanowire devices and fin devices are formed in a first region and a second region of a substrate. To form the devices, alternating layers of a first material and a second material are formed, inner spacers are formed adjacent to the layers of the first material, and then the layers of the first material are removed to form nanowires without removing the layers of the first material within the second region. Gate structures of gate dielectrics and gate electrodes are formed within the first region and the second region in order to form the nanowire devices in the first region and the fin devices in the second region.
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9.发明申请公开(公告)号：US20180350898A1
公开(公告)日：2018-12-06
申请号：US16100532
申请日：2018-08-10
发明人： Chewn-Pu Jou , Chih-Hsin Ko , Po-Wen Chiu , Chao-Ching Cheng , Chun-Chieh Lu , Chi-Feng Huang , Huan-Neng Chen , Fu-Lung Hsueh , Clement Hsingjen Wann
IPC分类号： H01L49/02 , H01L23/532 , H01G4/005 , H01G4/008 , H01L23/528 , H01L23/522 , H01L21/768
CPC分类号： H01L28/75 , C01B2204/04 , C01B2204/32 , H01G4/005 , H01G4/008 , H01L21/76852 , H01L23/5223 , H01L23/5226 , H01L23/5283 , H01L23/53214 , H01L23/53228 , H01L23/53257 , H01L23/53266 , H01L23/53276 , H01L2924/0002 , H01L2924/00
摘要： A capacitor includes a first graphene structure having a first plurality of graphene layers. The capacitor further includes a dielectric layer over the first graphene structure. The capacitor further includes a second graphene structure over the dielectric layer, wherein the second graphene structure has a second plurality of graphene layers.
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公开(公告)号：US20240324228A1
公开(公告)日：2024-09-26
申请号：US18679408
申请日：2024-05-30
IPC分类号： H10B43/35 , H01L29/08 , H01L29/165 , H01L29/66 , H01L29/78 , H01L29/792
CPC分类号： H10B43/35 , H01L29/0847 , H01L29/165 , H01L29/66636 , H01L29/66795 , H01L29/66833 , H01L29/7848 , H01L29/7851 , H01L29/792
摘要： A memory array and a structure of the memory array are provided. The memory array includes flash transistors, word lines and bit lines. The flash transistors are arranged in columns and rows. The flash transistors in each column are in serial connection with one another. The word lines are respectively coupled to gate terminals of a row of the flash transistors. The bit lines are respectively coupled to opposite ends of a column of the flash transistors. Band-to-band tunneling current at a selected flash transistor is utilized as read current during a read operation. The BTB tunneling current flows from one of the source/drain terminals of the selected flash transistor to the substrate, rather than flowing from one of the source/drain terminals to the other. As a result, charges stored in multiple programming sites of each flash transistor can be respectively sensed.
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