公开(公告)号：US20240224517A1

公开(公告)日：2024-07-04

申请号：US18093199

申请日：2023-01-04

申请人： YANGTZE MEMORY TECHNOLOGIES CO., LTD.

发明人： Yang Chen ,  Di Wang ,  Jingtao Xie ,  Qingfu Zhang ,  Zhiliang Xia ,  Zongliang Huo

IPC分类号： H10B43/27 ,  H10B41/27

CPC分类号： H10B43/27 ,  H10B41/27

摘要： A method for forming a three-dimensional (3D) memory device is disclosed. A stack structure including interleaved first dielectric layers and second dielectric layers is formed. Channel structures extending through the first dielectric layers and the second dielectric layers in a first region of the stack structure are formed. All the second dielectric layers in the first region and parts of the second dielectric layers in a second region of the stack structure are replaced with conductive layers. Word line pick-up structures extending through the first dielectric layers and remainders of the second dielectric layers in the second region of the stack structure are formed at different depths. A portion of the second dielectric layers in the second region that is closest to the opening is converted into a dielectric material different from the material of the second dielectric layers.

公开(公告)号：US20240206148A1

公开(公告)日：2024-06-20

申请号：US18089472

申请日：2022-12-27

申请人： YANGTZE MEMORY TECHNOLOGIES CO., LTD.

发明人： Kun Zhang ,  Yuancheng Yang ,  Dongxue Zhao ,  Tao Yang ,  Lei Liu ,  Di Wang ,  Wenxi Zhou ,  Zhiliang Xia ,  Zongliang Huo

IPC分类号： H10B12/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC分类号： H01L27/10802 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/1436

摘要： A memory device includes a first semiconductor layer, a first memory array, a second memory array, and a first peripheral circuit. The first memory array is disposed on a first side of the first semiconductor layer. The first memory array includes first memory cells, and first split structures. The second memory array is disposed on a second side of the first semiconductor layer opposite to the first side. The second memory array includes second memory cells, and second split structures. The first peripheral circuit including a first peripheral device disposed on the first memory array.

公开(公告)号：US20240196607A1

公开(公告)日：2024-06-13

申请号：US18234329

申请日：2023-08-15

申请人： Yangtze Memory Technologies Co., Ltd.

发明人： Zongliang Huo ,  Lei Xue ,  Wenbin Zhou ,  Zhengliang Xia ,  Han Yang ,  Xinwei Zou

IPC分类号： H10B43/27 ,  H10B41/27

CPC分类号： H10B43/27 ,  H10B41/27

摘要： 3D memory devices are disclosed. In an implementation, a 3D memory device includes a stack structure having a core area and a staircase area. The core area includes conductive layers interleaved with first dielectric layers. Each stair of the staircase area has a different number of conductive layers interleaved with a different number of first dielectric layers. The staircase area has contact structures that penetrate through the first surface, a respective one of the stairs, and dielectric material. Each of the contact structures is electrically connected to a contacting conductive layer of the different number of conductive layers of one of the stairs. The staircase area has second dielectric layers, each of which isolates a remainder of the different number of conductive layers of the respective one of the stairs other than the contacting conductive layer from a respective contact structure.

公开(公告)号：US20240098989A1

公开(公告)日：2024-03-21

申请号：US17948549

申请日：2022-09-20

申请人： YANGTZE MEMORY TECHNOLOGIES CO., LTD.

发明人： Zhengliang Xia ,  Wenbin Zhou ,  Zongliang Huo ,  Zhaohui Tang

IPC分类号： H01L27/11556 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582

CPC分类号： H01L27/11556 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582

摘要： A semiconductor device includes a plurality of memory blocks. Each memory block includes a memory deck including interleaved first conductor layers and first dielectric layers, and a separation structure extending to separate two adjacent memory blocks. Each separation structure includes a dielectric stack including interleaved third dielectric layers and fourth dielectric layers. The third dielectric layers are in contact with the first dielectric layers, and the fourth dielectric layers are in contact with the first conductor layers.

公开(公告)号：US11903195B2

公开(公告)日：2024-02-13

申请号：US18156619

申请日：2023-01-19

申请人： Yangtze Memory Technologies Co., Ltd.

发明人： Jia He ,  Haihui Huang ,  Fandong Liu ,  Yaohua Yang ,  Peizhen Hong ,  Zhiliang Xia ,  Zongliang Huo ,  Yaobin Feng ,  Baoyou Chen ,  Qingchen Cao

IPC分类号： H10B43/20 ,  H01L29/66 ,  H01L29/792 ,  H10B43/27 ,  H10B43/35 ,  H01L21/28

CPC分类号： H10B43/20 ,  H01L29/40117 ,  H01L29/66833 ,  H01L29/792 ,  H10B43/27 ,  H10B43/35

摘要： Embodiments of semiconductor devices and methods for forming the semiconductor devices are disclosed. In an example, a method for forming device openings includes forming a material layer over a first region and a second region of a substrate, the first region being adjacent to the second region, forming a mask layer over the material layer, the mask layer covering the first region and the second region, and forming a patterning layer over the mask layer. The patterning layer covers the first region and the second region and including openings corresponding to the first region. The plurality of openings includes a first opening adjacent to a boundary between the first region and the second region and a second opening further away from the boundary. Along a plane parallel to a top surface of the substrate, a size of the first opening is greater than a size of the second opening.

公开(公告)号：US20230413560A1

公开(公告)日：2023-12-21

申请号：US18236815

申请日：2023-08-22

申请人： YANGTZE MEMORY TECHNOLOGIES CO., LTD.

发明人： Qiang Xu ,  Fandong Liu ,  Zongliang Huo ,  Zhiliang Xia ,  Yaohua Yang ,  Peizhen Hong ,  Wenyu Hua ,  Jia He

IPC分类号： H10B43/27 ,  H10B43/10 ,  H10B43/30 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50 ,  H01L21/02 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L29/08 ,  H01L29/10

CPC分类号： H10B43/27 ,  H01L21/28568 ,  H10B43/30 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50 ,  H01L21/02164 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/528 ,  H01L29/0847 ,  H01L29/1037 ,  H01L21/02271 ,  H01L21/0262 ,  H10B43/10

摘要： A memory device includes a substrate, a stack over the substrate, and a gate line slit extending along a first direction and dividing the stack into two portions. The stack includes a connection portion that connects the two portions of the stack. The connection portion includes at least two sub-connection portions along a second direction perpendicular to the first direction. The gate line slit includes at least two portions along the first direction. Each sub-connection portion is between adjacent two portions of the gate line slit.

公开(公告)号：US20230361031A1

公开(公告)日：2023-11-09

申请号：US17738786

申请日：2022-05-06

申请人： Yangtze Memory Technologies Co., Ltd.

发明人： Lei LIU ,  Yuancheng Yang ,  Wenxi Zhou ,  Kun Zhang ,  Di Wang ,  Tao Yang ,  Dongxue Zhao ,  Zhiliang Xia ,  Zongliang Huo

IPC分类号： H01L23/528 ,  H01L27/11551 ,  H01L27/11578

CPC分类号： H01L23/5283 ,  H01L27/11551 ,  H01L27/11578

摘要： Embodiments of three-dimensional memory devices and fabricating methods thereof are disclosed. One disclosed method for forming a memory structure comprises: forming a bottom conductive layer on a substrate; forming a dielectric stack on the bottom conductive layer, the dielectric stack comprising a plurality of alternatively arranged first dielectric layers and second dielectric layers; forming an opening penetrating the dielectric stack and exposing the bottom conductive layer; forming a cap layer on a bottom of the opening; forming a cylindrical body and a top contact on the cap layer and in the opening; and replacing the plurality of second dielectric layers with conductive layers.

公开(公告)号：US20230354579A1

公开(公告)日：2023-11-02

申请号：US17731530

申请日：2022-04-28

申请人： Yangtze Memory Technologies Co., Ltd.

发明人： Yuancheng YANG ,  Dongxue Zhao ,  Tao Yang ,  Lei Liu ,  Di Wang ,  Kun Zhang ,  Wenxi Zhou ,  Zhiliang Xia ,  Zongliang Huo

IPC分类号： H01L27/108

CPC分类号： H01L27/10802

摘要： A three-dimensional (3D) memory device includes a memory cell, a top contact coupled to the memory cell, and a bottom contact coupled to the memory cell. The memory cell can include a pillar, an insulating layer surrounding the pillar, a first gate contact coupled to a word line, a second gate contact coupled to a plate line, and an annular dielectric layer within a portion of the pillar. The annular dielectric layer can increase a retention time of electrical charge in the pillar. The 3D memory device can utilize dynamic flash memory (DFM), increase retention times, decrease refresh rates, increase a floating body effect, decrease manufacturing defects, decrease leakage current, decrease junction current, decrease power consumption, increase an upper limit of charge density in the pillar, dynamically adjust a length of the plate line, and decrease parasitic resistance.

公开(公告)号：US11647632B2

公开(公告)日：2023-05-09

申请号：US17085305

申请日：2020-10-30

申请人： YANGTZE MEMORY TECHNOLOGIES CO., LTD.

发明人： Kun Zhang ,  Linchun Wu ,  Zhong Zhang ,  Wenxi Zhou ,  Zongliang Huo

IPC分类号： H01L27/1158 ,  H01L25/18 ,  H01L21/768 ,  H01L23/00 ,  H01L25/00 ,  H01L27/11582

CPC分类号： H01L27/11582 ,  H01L21/76898 ,  H01L24/08 ,  H01L24/32 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/32145

摘要： Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory stack, a first semiconductor layer, a supporting structure, a second semiconductor layer, and a plurality of channel structures. The memory stack includes vertically interleaved conductive layers and dielectric layers and has a core array region and a staircase region in a plan view. The first semiconductor layer is above and overlaps the core array region of the memory stack. The supporting structure is above and overlaps the staircase region of the memory stack. The supporting structure and the first semiconductor layer are coplanar. The second semiconductor layer is above and in contact with the first semiconductor layer and the supporting structure. Each channel structure extends vertically through the core array region of the memory stack and the first semiconductor layer into the second semiconductor layer.

公开(公告)号：US20230132574A1

公开(公告)日：2023-05-04

申请号：US17539818

申请日：2021-12-01

申请人： YANGTZE MEMORY TECHNOLOGIES CO., LTD.

发明人： Dongxue Zhao ,  Tao Yang ,  Zhiliang Xia ,  Zongliang Huo

IPC分类号： H01L27/108 ,  H01L29/78 ,  H01L29/66 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

摘要： In certain aspects, a memory device includes a vertical transistor including a semiconductor body extending in a first direction, a stack structure including interleaved dielectric layers and conductive layers each extending perpendicularly to the first direction, an electrode layer including a conductive material and coupled to a first end of the semiconductor body, and a storage layer over the electrode layer. The electrode layer and the storage layer extend in the first direction through the stack structure.