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1.发明公开公开(公告)号：US20240196607A1
公开(公告)日：2024-06-13
申请号：US18234329
申请日：2023-08-15
发明人： Zongliang Huo , Lei Xue , Wenbin Zhou , Zhengliang Xia , Han Yang , Xinwei Zou
摘要： 3D memory devices are disclosed. In an implementation, a 3D memory device includes a stack structure having a core area and a staircase area. The core area includes conductive layers interleaved with first dielectric layers. Each stair of the staircase area has a different number of conductive layers interleaved with a different number of first dielectric layers. The staircase area has contact structures that penetrate through the first surface, a respective one of the stairs, and dielectric material. Each of the contact structures is electrically connected to a contacting conductive layer of the different number of conductive layers of one of the stairs. The staircase area has second dielectric layers, each of which isolates a remainder of the different number of conductive layers of the respective one of the stairs other than the contacting conductive layer from a respective contact structure.
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公开(公告)号：US20240164100A1
公开(公告)日：2024-05-16
申请号：US18296222
申请日：2023-04-05
发明人： Mingkang Zhang , Liang Xiao , Yi Zhao , Shu Wu , Wenbin Zhou
IPC分类号： H10B43/27
CPC分类号： H10B43/27
摘要： Embodiments of 3D memory devices and methods for forming the same are disclosed. In one example, a 3D memory device includes a multi-layer stacked structure, where the multi-layer stacked structure includes a plurality of alternately stacked conductive layers and dielectric layers. The 3D memory device further includes a semiconductor layer over the multi-layer stacked structure, and a plurality of channel structures penetrating into the multi-layer stacked structure and the semiconductor layer. A first end of each channel structure is located within the semiconductor layer, and the first ends of the channel structures are aligned with one another.
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公开(公告)号：US20240098989A1
公开(公告)日：2024-03-21
申请号：US17948549
申请日：2022-09-20
发明人： Zhengliang Xia , Wenbin Zhou , Zongliang Huo , Zhaohui Tang
IPC分类号： H01L27/11556 , H01L27/11519 , H01L27/11526 , H01L27/11565 , H01L27/11573 , H01L27/11582
CPC分类号： H01L27/11556 , H01L27/11519 , H01L27/11526 , H01L27/11565 , H01L27/11573 , H01L27/11582
摘要： A semiconductor device includes a plurality of memory blocks. Each memory block includes a memory deck including interleaved first conductor layers and first dielectric layers, and a separation structure extending to separate two adjacent memory blocks. Each separation structure includes a dielectric stack including interleaved third dielectric layers and fourth dielectric layers. The third dielectric layers are in contact with the first dielectric layers, and the fourth dielectric layers are in contact with the first conductor layers.
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公开(公告)号：US20220085042A1
公开(公告)日：2022-03-17
申请号：US17532675
申请日：2021-11-22
发明人： Wenxiang XU , Haohao Yang , Pan Huang , Ping Yan , Zongliang Huo , Wenbin Zhou , Wei Xu
IPC分类号： H01L27/11539 , H01L23/522 , H01L27/11519 , H01L27/11556 , H01L27/11565 , H01L27/11582
摘要： Embodiments of three-dimensional (3D) memory devices and fabricating methods thereof are disclosed. The method includes: forming an alternating dielectric stack on a substrate; forming a structure strengthen plug in an upper portion of the alternating dielectric stack, wherein the structure strengthen plug has a narrow support body and two enlarged connecting portions; forming a gate line silt in the alternating dielectric stack to expose a sidewall of one enlarged connecting portion of the structure strengthen plug; and forming a gate line slit structure in the gate line slit including an enlarged end portion connected to the one enlarged connecting portion of the structure strengthen plug.
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公开(公告)号：US11183512B2
公开(公告)日：2021-11-23
申请号：US16670571
申请日：2019-10-31
发明人： Zongliang Huo , Haohao Yang , Wei Xu , Ping Yan , Pan Huang , Wenbin Zhou
IPC分类号： H01L27/11582 , H01L21/311 , H01L27/11556
摘要： Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a 3D memory device includes a memory stack, a plurality of channel structures, a slit structure, and a source structure. The memory stack may be over a substrate and may include interleaved a plurality of conductor layers and a plurality of insulating layers extending laterally in the memory stack. The plurality of channel structures may extend vertically through the memory stack into the substrate. The slit structure may extend vertically and laterally in the memory stack and divide the plurality of memory cells into at least one memory block. The slit structure may include a plurality of protruding portions and a plurality of recessed portions arranged vertically along a sidewall of the slit structure.
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公开(公告)号：US11094712B2
公开(公告)日：2021-08-17
申请号：US16670579
申请日：2019-10-31
发明人： Zongliang Huo , Haohao Yang , Wei Xu , Ping Yan , Pan Huang , Wenbin Zhou
IPC分类号： H01L27/11582 , H01L23/522 , H01L27/11565 , H01L27/1157 , H01L23/528
摘要： Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a 3D memory device includes a stack structure and at least one source structure extending vertically and laterally and dividing the stack structure into a plurality of block regions. The stack structure may include a plurality of conductor layers and a plurality of insulating layers interleaved over a substrate. The at least one source structure includes at least one support structure extending along the vertical direction to the substrate, the at least one support structure being in contact with at least a sidewall of the respective source structure.
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公开(公告)号：US20210066336A1
公开(公告)日：2021-03-04
申请号：US16689513
申请日：2019-11-20
发明人： Qingqing Wang , Wei Xu , Pan Huang , Ping Yan , Zongliang Huo , Wenbin Zhou
IPC分类号： H01L27/11582 , H01L23/528 , H01L27/1157 , H01L27/11565
摘要： A three-dimensional (3D) memory device includes a memory stack over a substrate. The memory stack includes interleaved conductor layers and insulating layers. The 3D memory device also includes channel structures extending vertically in the memory stack. The 3D memory device further includes a source structure extending in the memory stack. The source structure includes first and second source contacts separated by a support structure. The source structure also includes an adhesion layer. At least a portion of the adhesion layer is between the first and second source contacts and conductively connects the first and second source contacts.
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8.发明申请公开(公告)号：US20190157298A1
公开(公告)日：2019-05-23
申请号：US16166655
申请日：2018-10-22
发明人： Zongliang Huo , Wenbin Zhou , Zhiguo Zhao , Zhaoyun Tang , Hai Lin Xiong
IPC分类号： H01L27/11595 , H01L27/11575
CPC分类号： H01L27/11595 , H01L27/11548 , H01L27/11575
摘要： Embodiments of a semiconductor memory device include a substrate having a first region with peripheral devices, a second region with one or more memory arrays, and a third region between the first and the second regions. The semiconductor memory device also includes a protective structure for peripheral devices. The protective structure for peripheral devices of the semiconductor memory device includes a first dielectric layer and a barrier layer disposed on the first dielectric layer. The protective structure for peripheral devices of the semiconductor memory device further includes a dielectric spacer formed on a sidewall of the barrier layer and a sidewall of the first dielectric layer, wherein the protective structure is disposed over the first region and at least a portion of the third region.
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公开(公告)号：US20190157287A1
公开(公告)日：2019-05-23
申请号：US16149155
申请日：2018-10-02
发明人： ZONGLIANG HUO , Deqin Yu , Wenbin Zhou , Yong Hui Gao
IPC分类号： H01L27/11573 , H01L27/12 , H01L27/11524 , H01L27/11556 , H01L27/11529 , H01L27/1157 , H01L27/11582
摘要： A three-dimensional (3D) memory structure and a manufacturing method thereof are provided. The method includes the following steps. A 3D memory unit is formed on a first region of a substrate. A first insulation layer is formed on the first region and a second region of the substrate. A first planarization process is performed to the first insulation layer. The top surface of the first insulation layer on the first region and the top surface of the first insulation layer on the second region are coplanar after the first planarization process. A peripheral circuit is formed on the second region after the first planarization process. The influence of the process for forming the 3D memory unit on the peripheral circuit may be avoided. The manufacturing yield, the electrical performance, and the reliability of the 3D memory structure may be enhanced accordingly.
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公开(公告)号：US11785772B2
公开(公告)日：2023-10-10
申请号：US17528095
申请日：2021-11-16
发明人： Wenxiang Xu , Wei Xu , Pan Huang , Ping Yan , Zongliang Huo , Wenbin Zhou , Ji Xia
IPC分类号： H10B43/10 , H01L21/02 , H01L21/311 , H01L21/768 , H10B43/27
CPC分类号： H10B43/10 , H01L21/02164 , H01L21/31116 , H01L21/76802 , H01L21/76831 , H01L21/76834 , H01L21/76877 , H10B43/27 , H01L21/0228
摘要： Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a 3D memory device includes a memory stack having interleaved a plurality of conductor layers and a plurality of insulating layers, a plurality of channel structures extending in the memory stack, and a source structure extending in the memory stack. The source structure includes a plurality of source contacts each in a respective insulating structure. Two adjacent source contacts are conductively connected to one another by a connection layer, the connection layer includes a pair of first portions being over the two adjacent ones of the plurality of source contacts and a second portion between the pair of first portions. A support structure is between the two adjacent source contacts. The support structure includes a cut structure over interleaved a plurality of conductor portions and a plurality of insulating portions.
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