公开(公告)号：US20240407168A1

公开(公告)日：2024-12-05

申请号：US18378513

申请日：2023-10-10

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Quan Zhang ,  Lei Xue ,  Yanwei Shi ,  Wenshan Xu ,  Chao Sun ,  Liang Chen ,  Boru Xie

IPC: H10B43/35 ,  H01L25/065 ,  H01L29/66 ,  H01L29/78 ,  H10B41/20 ,  H10B41/35 ,  H10B43/20

Abstract: The present disclosure provides a semiconductor device and a manufacturing method thereof, as well as a memory system. The semiconductor device includes a first semiconductor structure comprising a first well region and transistors in the first well region, and a second semiconductor structure bonded with the first semiconductor structure and including a second well region, and fin field effect transistors in the second well region. Each fin field effect transistor includes a fin structure, a gate oxide layer in contact with a top surface and side surfaces of the fin structure, and a gate layer covering the gate oxide layer.

公开(公告)号：US11652042B2

公开(公告)日：2023-05-16

申请号：US17147409

申请日：2021-01-12

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Lei Xue ,  Wei Liu ,  Liang Chen

IPC: H01L23/522 ,  H01L21/768 ,  H01L49/02 ,  H01L27/11582 ,  H01L27/1157

CPC classification number: H01L23/5223 ,  H01L21/76832 ,  H01L27/1157 ,  H01L27/11582 ,  H01L28/40 ,  H01L28/56

Abstract: Embodiments of semiconductor devices and methods for forming the same are disclosed. In an example, a semiconductor device includes at least one dielectric layer pair including a first dielectric layer and a second dielectric layer different from the first dielectric layer, an interlayer dielectric (ILD) layer in contact with the at least one dielectric layer pair, and one or more capacitors each extending vertically through the ILD layer and in contact with the at least one dielectric layer pair.

公开(公告)号：US11563021B2

公开(公告)日：2023-01-24

申请号：US16892439

申请日：2020-06-04

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Bo Huang ,  Lei Xue ,  Jiaqian Xue ,  Tingting Gao ,  Wanbo Geng ,  Xiaoxin Liu

IPC: H01L27/1157 ,  H01L27/11524 ,  H01L27/11539 ,  H01L27/11551 ,  H01L27/11578

Abstract: A method for forming a memory device includes providing an initial semiconductor structure, including a base substrate; a first sacrificial layer formed on the base substrate; a stack structure, disposed on the first sacrificial layer; a plurality of channels, formed through the stack structure and the first sacrificial layer; and a gate-line trench, formed through the stack structure and exposing the first sacrificial layer. The method also includes forming at least one protective layer on the sidewalls of the gate-line trench; removing the first sacrificial layer to expose a portion of each of the plurality of channels and the surfaces of the base substrate, using the at least one protective layer as an etch mask; and forming an epitaxial layer on the exposed surfaces of the base substrate and the plurality of channels.

公开(公告)号：US20220367394A1

公开(公告)日：2022-11-17

申请号：US17482074

申请日：2021-09-22

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Chao Sun ,  Liang Chen ,  Wenshan Xu ,  Wei Liu ,  Ning Jiang ,  Lei Xue ,  Wu Tian

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure including an array of memory cells, a second semiconductor structure including a peripheral circuit, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The peripheral circuit includes a 3D transistor. The array of memory cells is coupled to the peripheral circuit across the bonding interface.

公开(公告)号：US20220149070A1

公开(公告)日：2022-05-12

申请号：US17117744

申请日：2020-12-10

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Wanbo Geng ,  Lei Xue ,  Xiaoxin Liu ,  Tingting Gao

IPC: H01L27/11582 ,  H01L27/1157

Abstract: A first opening extending vertically through a dielectric stack is formed above a substrate. The dielectric stack includes vertically interleaved dielectric layers and sacrificial layers. Parts of the sacrificial layers facing the opening are removed to form a plurality of first recesses. A plurality of stop structures are formed along sidewalls of the plurality of first recesses. A plurality of storage structures are formed over the plurality of stop structures in the plurality of first recesses. The plurality of sacrificial layers are removed to expose the plurality of stop structures from a plurality of second recesses opposing the plurality of first recesses. The plurality of stop structures are removed to expose the plurality of storage structures. A plurality of blocking structures are formed over the plurality of storage structures in the plurality of second recesses.

公开(公告)号：US20220068797A1

公开(公告)日：2022-03-03

申请号：US17488287

申请日：2021-09-28

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Lei Xue ,  Wei Liu ,  Liang Chen

IPC: H01L23/522 ,  H01L49/02 ,  H01L21/768

Abstract: Embodiments of semiconductor devices and methods for forming the same are disclosed. In an example, a semiconductor device includes at least one dielectric layer pair including a first dielectric layer and a second dielectric layer different from the first dielectric layer, an interlayer dielectric (ILD) layer in contact with the at least one dielectric layer pair, and one or more capacitors each extending vertically through the ILD layer and in contact with the at least one dielectric layer pair.

公开(公告)号：US20220068795A1

公开(公告)日：2022-03-03

申请号：US17147409

申请日：2021-01-12

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Lei Xue ,  Wei Liu ,  Liang Chen

IPC: H01L23/522 ,  H01L49/02 ,  H01L21/768

Abstract: Embodiments of semiconductor devices and methods for forming the same are disclosed. In an example, a semiconductor device includes at least one dielectric layer pair including a first dielectric layer and a second dielectric layer different from the first dielectric layer, an interlayer dielectric (ILD) layer in contact with the at least one dielectric layer pair, and one or more capacitors each extending vertically through the ILD layer and in contact with the at least one dielectric layer pair.

公开(公告)号：US20220013537A1

公开(公告)日：2022-01-13

申请号：US17085366

申请日：2020-10-30

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Wanbo Geng ,  Lei Xue ,  Xiaoxin Liu ,  Tingting Gao ,  Weihua Cheng

IPC: H01L27/11582 ,  H01L27/11565

Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A channel hole extending vertically above a substrate and having a plum blossom shape in a plan view is formed. A continuous blocking layer, a continuous charge trapping layer, and a continuous tunneling layer each following the plum blossom shape are formed from outside to inside in this order along sidewalls of the channel hole. A plurality of separate semiconductor channels each disposed over part of the continuous tunneling layer at a respective apex of the plum blossom shape are formed.

公开(公告)号：US11094714B2

公开(公告)日：2021-08-17

申请号：US16729865

申请日：2019-12-30

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Liang Chen ,  Lei Xue ,  Wei Liu ,  Shi Qi Huang

IPC: H01L27/115 ,  H01L27/11582 ,  H01L21/02 ,  H01L21/768 ,  H01L23/48 ,  H01L23/528 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00 ,  H01L27/11573 ,  H01L21/3105 ,  H01L21/311

Abstract: A method for forming a gate structure of a 3D memory device is provided. The method comprises forming an array wafer including a periphery region and a staircase and array region. A process of forming an array wafer comprises forming an alternating dielectric etch stop structure on a first substrate in the periphery region, forming an array device on the first substrate in the staircase and array region, and forming at least one first vertical through contact in the periphery region and in contact with the alternating dielectric etch stop structure. The method further comprises forming a CMOS wafer and bonding the array wafer and the CMOS wafer. The method further comprises forming at least one through substrate contact penetrating the first substrate and the alternating dielectric etch stop structure, and in contact with the at least one first vertical through contact.

公开(公告)号：US10854628B2

公开(公告)日：2020-12-01

申请号：US16292212

申请日：2019-03-04

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Lan Yao ,  Lei Xue

IPC: H01L29/792 ,  H01L27/11582 ,  H01L27/1157 ,  H01L21/02 ,  H01L21/28

Abstract: A three-dimensional (3D) memory device and a manufacturing method thereof are provided. The method includes the following steps. An alternating dielectric stack is formed on a substrate. A vertical structure is formed penetrating the alternating dielectric stack in a vertical direction. A bottom dielectric layer of the alternating dielectric stack is removed. An epitaxial layer is formed between the substrate and the alternating dielectric stack after removing the bottom dielectric layer. An insulating layer is formed on the epitaxial layer. The insulating layer is located between the epitaxial layer and the alternating dielectric stack. The influence of the step of forming the vertical structure on the epitaxial layer may be avoided, and defects at the interface between the epitaxial layer and the bottom dielectric layer may be avoided accordingly.