公开(公告)号：US20220367503A1

公开(公告)日：2022-11-17

申请号：US17481971

申请日：2021-09-22

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Chao Sun ,  Liang Chen ,  Wenshan Xu ,  Wei Liu ,  Ning Jiang ,  Lei Xue ,  Wu Tian

IPC: H01L27/11573 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582

Abstract: In certain aspects, a memory device includes an array of memory cells and a plurality of peripheral circuits coupled to the array of memory cells and configured to control the array of memory cells. A first peripheral circuit of the plurality of peripheral circuits includes a first three-dimensional (3D) transistor. The first 3D transistor includes a 3D semiconductor body, and a gate structure in contact with a plurality of sides of the 3D semiconductor body. The gate structure includes a gate dielectric and a gate electrode. The gate electrode includes a metal, and the gate dielectric has a thickness between 1.8 nm and 10 nm.

公开(公告)号：US20220013631A1

公开(公告)日：2022-01-13

申请号：US17483760

申请日：2021-09-23

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Chao Sun

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: The present disclosure provides a method for manufacturing a high voltage semiconductor device which includes providing a semiconductor substrate; forming at least one first isolation structure and at least one second isolation structure in the semiconductor substrate; forming a gate structure on the semiconductor substrate and at a side of the at least one first isolation structure; and forming at least one first drift region in the semiconductor substrate at a side of the gate structure, in which a bottom of the at least one first isolation structure and a bottom of the at least one second isolation structure are deeper than a bottom of the first drift region.

公开(公告)号：US20200279915A1

公开(公告)日：2020-09-03

申请号：US16540069

申请日：2019-08-14

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Chao Sun

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66

Abstract: High voltage semiconductor device and manufacturing method thereof are disclosed. The high voltage semiconductor device includes a semiconductor substrate, a gate structure on the semiconductor substrate, at least one first isolation structure, and at least on first drift region. The first isolation structure and the first drift region are disposed in the semiconductor substrate at a side of the gate structure. The first isolation structure vertically penetrates through the first drift region.

公开(公告)号：US20240407168A1

公开(公告)日：2024-12-05

申请号：US18378513

申请日：2023-10-10

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Quan Zhang ,  Lei Xue ,  Yanwei Shi ,  Wenshan Xu ,  Chao Sun ,  Liang Chen ,  Boru Xie

IPC: H10B43/35 ,  H01L25/065 ,  H01L29/66 ,  H01L29/78 ,  H10B41/20 ,  H10B41/35 ,  H10B43/20

Abstract: The present disclosure provides a semiconductor device and a manufacturing method thereof, as well as a memory system. The semiconductor device includes a first semiconductor structure comprising a first well region and transistors in the first well region, and a second semiconductor structure bonded with the first semiconductor structure and including a second well region, and fin field effect transistors in the second well region. Each fin field effect transistor includes a fin structure, a gate oxide layer in contact with a top surface and side surfaces of the fin structure, and a gate layer covering the gate oxide layer.

公开(公告)号：US20240381620A1

公开(公告)日：2024-11-14

申请号：US18203574

申请日：2023-05-30

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Chao Sun ,  Ning Jiang ,  Wei Liu

IPC: H10B12/00

Abstract: Three-dimensional (3D) semiconductor devices and fabricating methods are disclosed. The semiconductor device includes an array of vertical transistors. Each vertical transistor includes a semiconductor body extending in a vertical direction, and an all-around gate structure laterally surrounding the semiconductor body. Each row of the vertical transistors in a first lateral direction share a common word line extending in the first lateral direction and comprising the all-around gate structures of the row of the vertical transistors. Adjacent rows of the vertical transistors are misaligned along a second lateral direction perpendicular with the first lateral direction. The array of vertical transistors are aligned along a third lateral direction different from the first lateral direction and the second lateral direction.

公开(公告)号：US20230371241A1

公开(公告)日：2023-11-16

申请号：US18204819

申请日：2023-06-01

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Chao Sun ,  Ning Jiang ,  Wei Liu

IPC: H10B12/00

CPC classification number: H10B12/395 ,  H10B12/482 ,  H10B12/488 ,  H10B12/485

Abstract: Three-dimensional (3D) semiconductor devices and fabricating methods are provided. In some implementations, a 3D semiconductor device includes: an array of vertical transistors each comprising a semiconductor body extending in a vertical direction; a plurality of word lines each extending in a first lateral direction, wherein each word line is shared by a row of the vertical transistors arranged along the first lateral direction; and a plurality of bit lines each extending in a second lateral direction perpendicular to the first lateral direction; wherein the semiconductor bodies are further arranged along a third lateral direction different from the first lateral direction and the second lateral direction.

公开(公告)号：US20220367394A1

公开(公告)日：2022-11-17

申请号：US17482074

申请日：2021-09-22

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Chao Sun ,  Liang Chen ,  Wenshan Xu ,  Wei Liu ,  Ning Jiang ,  Lei Xue ,  Wu Tian

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure including an array of memory cells, a second semiconductor structure including a peripheral circuit, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The peripheral circuit includes a 3D transistor. The array of memory cells is coupled to the peripheral circuit across the bonding interface.

公开(公告)号：US20200279914A1

公开(公告)日：2020-09-03

申请号：US16540067

申请日：2019-08-14

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Chao Sun

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66

Abstract: High voltage semiconductor device and manufacturing method thereof are disclosed. The high voltage semiconductor device includes a semiconductor substrate, a gate structure, at least one first isolation structure and at least one second isolation structure, and at least one first drift region. The gate structure is disposed on the semiconductor substrate. The first isolation structure and the second isolation structure are disposed in an active area of the semiconductor substrate at a side of the gate structure. An end of the second isolation structure is disposed between the first isolation structure and the gate structure, and an end of the first isolation structure is disposed between the first doped region and the second isolation structure. A bottom of the at least one first isolation structure and a bottom of the at least one second isolation structure are deeper than a bottom of the first drift region.

公开(公告)号：US12063784B2

公开(公告)日：2024-08-13

申请号：US17482046

申请日：2021-09-22

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Liang Chen ,  Chao Sun ,  Wei Liu ,  Wenshan Xu ,  Wu Tian ,  Ning Jiang ,  Lei Xue

IPC: H10B43/40 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

CPC classification number: H10B43/40 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: In certain aspects, a memory device includes an array of memory cells, a plurality of word lines coupled to the array of memory cells, and a plurality of peripheral circuits coupled to the array of memory cells and configured to control the array of memory cells. A first peripheral circuit of the plurality of peripheral circuits includes a first three-dimensional (3D) transistor coupled to the array of memory cells through at least one of the plurality of word lines. The first 3D transistor includes a 3D semiconductor body, and a gate structure in contact with a plurality of sides of the 3D semiconductor body. The gate structure includes a gate dielectric and a gate electrode.

公开(公告)号：US11769794B2

公开(公告)日：2023-09-26

申请号：US17483760

申请日：2021-09-23

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Chao Sun

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/762

CPC classification number: H01L29/0653 ,  H01L29/0611 ,  H01L29/66681 ,  H01L29/7816 ,  H01L21/762

Abstract: The present disclosure provides a method for manufacturing a high voltage semiconductor device which includes providing a semiconductor substrate; forming at least one first isolation structure and at least one second isolation structure in the semiconductor substrate; forming a gate structure on the semiconductor substrate and at a side of the at least one first isolation structure; and forming at least one first drift region in the semiconductor substrate at a side of the gate structure, in which a bottom of the at least one first isolation structure and a bottom of the at least one second isolation structure are deeper than a bottom of the first drift region.