公开(公告)号：US12052870B2

公开(公告)日：2024-07-30

申请号：US17495252

申请日：2021-10-06

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Zhong Zhang ,  Wenyu Hua ,  Bo Huang ,  Zhiliang Xia

IPC: H01L21/31 ,  H01L21/033 ,  H01L21/28 ,  H01L21/311 ,  H01L29/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L21/0337 ,  H01L21/31144 ,  H01L29/40117 ,  H10B43/10 ,  H10B43/35

Abstract: Embodiments of staircase structures of a three-dimensional memory device and fabrication method thereof are disclosed. The semiconductor structure includes a first and a second film stacks, wherein the first film stack is disposed over the second film stack and has M1 number of layers. The second film stack has M2 number of layers. M1 and M2 are whole numbers. The semiconductor structure also includes an upper staircase structure and a lower staircase structure, wherein the upper staircase structure is formed in the first film stack and the lower staircase structure is formed in the second film stack. The upper and lower staircase structures are next to each other with an offset.

公开(公告)号：US11563021B2

公开(公告)日：2023-01-24

申请号：US16892439

申请日：2020-06-04

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Bo Huang ,  Lei Xue ,  Jiaqian Xue ,  Tingting Gao ,  Wanbo Geng ,  Xiaoxin Liu

IPC: H01L27/1157 ,  H01L27/11524 ,  H01L27/11539 ,  H01L27/11551 ,  H01L27/11578

Abstract: A method for forming a memory device includes providing an initial semiconductor structure, including a base substrate; a first sacrificial layer formed on the base substrate; a stack structure, disposed on the first sacrificial layer; a plurality of channels, formed through the stack structure and the first sacrificial layer; and a gate-line trench, formed through the stack structure and exposing the first sacrificial layer. The method also includes forming at least one protective layer on the sidewalls of the gate-line trench; removing the first sacrificial layer to expose a portion of each of the plurality of channels and the surfaces of the base substrate, using the at least one protective layer as an etch mask; and forming an epitaxial layer on the exposed surfaces of the base substrate and the plurality of channels.

公开(公告)号：US20200273874A1

公开(公告)日：2020-08-27

申请号：US16422434

申请日：2019-05-24

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Zhong Zhang ,  Wenyu Hua ,  Bo Huang ,  Zhiliang Xia

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L21/28 ,  H01L21/311 ,  H01L21/033

Abstract: Embodiments of staircase structures of a three-dimensional memory device and fabrication method thereof are disclosed. The semiconductor structure includes a first and a second film stacks, wherein the first film stack is disposed over the second film stack and has M1 number of layers. The second film stack has M2 number of layers. M1 and M2 are whole numbers. The semiconductor structure also includes a first and a second staircase structures, wherein the first staircase structure is formed in the first film stack and the second staircase structure is formed in the second film stack. The first and second staircase structures are next to each other with an offset.

公开(公告)号：US11751385B2

公开(公告)日：2023-09-05

申请号：US17005612

申请日：2020-08-28

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Jiaqian Xue ,  Tingting Gao ,  Lei Xue ,  Wanbo Geng ,  Xiaoxin Liu ,  Bo Huang

IPC: H01L27/11582 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

Abstract: A method for forming a 3D memory device is provided. The method comprises forming a sacrificial layer on a substrate, forming an alternating dielectric stack on the sacrificial layer, forming a plurality of channel holes vertically penetrating the alternating dielectric stack and the sacrificial layer, and forming a first channel layer in each channel hole. The method further comprises forming a second channel layer on the first channel layer in each channel hole, such that a merging point of the second channel layer is higher than a bottom surface of the alternating dielectric stack. The method further comprises removing the sacrificial layer to form a horizontal trench, and forming a selective epitaxial growth layer in the horizontal trench.

公开(公告)号：US11462558B2

公开(公告)日：2022-10-04

申请号：US16422434

申请日：2019-05-24

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Zhong Zhang ,  Wenyu Hua ,  Bo Huang ,  Zhiliang Xia

IPC: H01L27/115 ,  H01L27/11582 ,  H01L21/28 ,  H01L21/033 ,  H01L21/311 ,  H01L27/11565 ,  H01L27/1157

Abstract: Embodiments of staircase structures of a three-dimensional memory device and fabrication method thereof are disclosed. The semiconductor structure includes a first and a second film stacks, wherein the first film stack is disposed over the second film stack and has M1 number of layers. The second film stack has M2 number of layers. M1 and M2 are whole numbers. The semiconductor structure also includes a first and a second staircase structures, wherein the first staircase structure is formed in the first film stack and the second staircase structure is formed in the second film stack. The first and second staircase structures are next to each other with an offset.

公开(公告)号：US12052866B2

公开(公告)日：2024-07-30

申请号：US17113662

申请日：2020-12-07

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Wanbo Geng ,  Lei Xue ,  Jiaqian Xue ,  Xiaoxin Liu ,  Tingting Gao ,  Bo Huang

IPC: H10B43/35 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

Abstract: The present disclosure provides a method of processing a semiconductor device having a stack formed over a source sacrificial layer above a substrate, a channel structure extending vertically through the stack and the source sacrificial layer, a gate line cut trench extending vertically through the stack, and a spacer layer covering uncovered top and side surfaces of the stack. The method can include exposing a lower sidewall of the channel structure by removing the source sacrificial layer, forming a protection layer on all uncovered surfaces, exposing a channel layer of the channel structure by removing a first portion of the protection layer and an insulating layer of the channel structure, forming an initial source connection layer over the exposed channel layer, exposing the substrate by removing a second portion of the protection layer, and forming a source connection layer over the initial source connection layer and the exposed substrate.