公开(公告)号：US11276632B2

公开(公告)日：2022-03-15

申请号：US16724889

申请日：2019-12-23

申请人： NEPES CO., LTD.

发明人： Gi Jo Jung ,  Chang Yong Jo ,  Young Mo Lee ,  Jung Sic Oh ,  Jong Ho Han

IPC分类号： H01L23/498 ,  H01L23/00 ,  H01L23/532

摘要： A semiconductor package includes a semiconductor chip including a chip pad on a first surface thereof, an external pad electrically connected to the chip pad of the semiconductor chip, an external connection terminal covering the external pad, and an intermediate layer between the external pad and the external connection terminal, the intermediate layer including a third metal material that is different from a first metal material included in the external pad and a second metal material included in the external connection terminal.

公开(公告)号：US20210193602A1

公开(公告)日：2021-06-24

申请号：US17121804

申请日：2020-12-15

申请人： Nepes CO., LTD.

发明人： Jun Kyu LEE ,  Su Yun Kim ,  Dong Hoon OH ,  Yong Tae KWON ,  Ju Hyun NAM

IPC分类号： H01L23/00

摘要： A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a lower structure including a semiconductor chip having a chip terminal; an external connection terminal connecting the semiconductor chip to an external device, and an intermediate connection structure including an upper surface and a lower surface opposite to the upper surface, and positioned between the lower structure and the external connection terminal.

公开(公告)号：US10964656B2

公开(公告)日：2021-03-30

申请号：US16427033

申请日：2019-05-30

申请人： Nepes CO., LTD.

发明人： Yong Tae Kwon ,  Hee Cheol Kim ,  Seung Jun Moon ,  Jini Shim

IPC分类号： H01L23/00

摘要： The present invention relates to a semiconductor package and a method of manufacturing the same. In a semiconductor package which electrically connects a semiconductor chip and a printed circuit board using a solder ball, the semiconductor package further includes a thermal buffer layer which is positioned on a semiconductor chip, absorbs and disperse heat generated by the semiconductor chip, increases a distance between the semiconductor chip and a printed circuit board to decrease a deviation of a heat conduction process, and has a thickness ranging from 7.5 to 50% of a diameter of a solder ball.

公开(公告)号：US20190229101A1

公开(公告)日：2019-07-25

申请号：US16242572

申请日：2019-01-08

申请人： NEPES CO., LTD.

发明人： Jun Kyu Lee

IPC分类号： H01L25/10 ,  H01L23/552 ,  H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L21/56

摘要： A semiconductor package includes a first package including a first semiconductor chip, a first encapsulation layer that covers the first semiconductor chip, and a first redistribution pattern connected to pads of the first semiconductor chip and a second package on the first package, the second package including a second semiconductor chip, a second encapsulation layer that covers the second semiconductor chip, and a second redistribution pattern connected to pads of the second semiconductor chip. The first redistribution pattern is connected to the second redistribution pattern through the first encapsulation layer.

公开(公告)号：US20170141043A1

公开(公告)日：2017-05-18

申请号：US15353730

申请日：2016-11-16

申请人： NEPES CO., LTD.

发明人： Yunmook PARK

IPC分类号： H01L23/538 ,  H01L21/768 ,  H01L21/311 ,  H01L25/065 ,  H01L23/31 ,  H01L21/56

CPC分类号： H01L23/5389 ,  H01L21/31133 ,  H01L21/565 ,  H01L21/568 ,  H01L21/76895 ,  H01L23/3128 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16235 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1815 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/3511

摘要： Disclosed are a semiconductor package including a through via and a method of manufacturing the same. The semiconductor package includes a frame having an accommodation part and configured to transmit an electrical signal between upper and lower portions thereof through a through via provided around the accommodation part, one or more semiconductor chips accommodated in the accommodation part, a wiring part provided below the frame and the semiconductor chips and configured to connect the through via to the semiconductor chips, an encapsulant molded to integrate the frame and the semiconductor chips, and a conductive ball or a conductive post connected to an upper portion of the through via.

公开(公告)号：US20160099210A1

公开(公告)日：2016-04-07

申请号：US14866725

申请日：2015-09-25

申请人： NEPES CO., LTD.

发明人： Yong-Tae KWON ,  Jun-Kyu LEE

IPC分类号： H01L23/522 ,  H01L25/07 ,  H01L23/528 ,  H01L21/768 ,  H01L23/532 ,  H01L23/10

CPC分类号： H01L23/528 ,  H01L21/486 ,  H01L21/568 ,  H01L21/76829 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/522 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24227 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/15311

摘要： Disclosed herein are a semiconductor package and a method of manufacturing the same, which allows a conductive path to be provided to connect upper and lower portions of the semiconductor package. A semiconductor package according to the present invention includes a semiconductor chip, a substrate including an accommodating portion to accommodate the semiconductor chip, a sealing material configured to mold the semiconductor chip and the substrate to be integrated, a through wiring configured to vertically pass through the substrate, a wiring portion configured to electrically connect the semiconductor chip and one side of the through wiring, and an external connection portion to electrically connected to the other side of the through wiring and configured to be able to be electrically connected to an outside, wherein a wiring layer of the wiring portion is provided to be connected to the through wiring.

摘要翻译： 这里公开了半导体封装及其制造方法，其允许提供导电路径以连接半导体封装的上部和下部。 根据本发明的半导体封装包括半导体芯片，包括容纳半导体芯片的容纳部分的基板，被配置为模制半导体芯片和要被集成的基板的密封材料，被配置为垂直穿过所述半导体芯片的通孔 基板，被配置为将所述半导体芯片和所述贯通布线的一侧电连接的布线部分和外部连接部分，以电连接到所述贯通布线的另一侧并且被配置为能够电连接到外部，其中 布线部分的布线层设置成连接到贯通布线。

公开(公告)号：US20150287681A1

公开(公告)日：2015-10-08

申请号：US14389763

申请日：2012-04-06

申请人： NEPES CO., LTD.

发明人： Say Hean Soh ,  Yuen Zien Siew ,  Chuan Wei Wong ,  Siew Boon Soh ,  Haoyang Chen

IPC分类号： H01L23/538 ,  H01L21/683 ,  H01L25/065 ,  H01L21/3213 ,  H01L25/00 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/02 ,  H01L21/56 ,  H01L21/768

CPC分类号： H01L23/5389 ,  H01L21/02068 ,  H01L21/31053 ,  H01L21/32115 ,  H01L21/3213 ,  H01L21/486 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/768 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68304 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2221/68377 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/2101 ,  H01L2224/211 ,  H01L2224/215 ,  H01L2224/82106 ,  H01L2224/96 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/01029 ,  H01L2924/01013 ,  H01L2224/19 ,  H01L2924/014 ,  H01L2924/00

摘要： Provided is a method of manufacturing a semiconductor package including a through wiring having precision and a low process defect. The method of manufacturing the semiconductor package includes preparing a conductive member; forming a plane part and projection parts projected from the plane part by removing portions of the conductive member; arranging the conductive member and a semiconductor chip, and forming a sealing member sealing the semiconductor chip and the conductive member; forming through wirings by exposing the projection parts of the conductive member from the sealing member; forming a re-wiring pattern layer which electrically connects the through wirings and the semiconductor chip; and forming external connection members which are electrically connected to the re-wiring pattern layer.

摘要翻译： 提供一种制造半导体封装的方法，该半导体封装包括具有精度和低工艺缺陷的贯通布线。 制造半导体封装的方法包括制备导电构件; 通过去除所述导电构件的部分，形成从所述平面部突出的平面部分和突出部分; 布置导电构件和半导体芯片，并形成密封半导体芯片和导电构件的密封构件; 通过使导电构件的突出部从密封构件露出而通过布线形成; 形成电连接所述贯通布线和所述半导体芯片的再布线图案层; 以及形成电连接到再布线图案层的外部连接构件。

公开(公告)号：US20140353823A1

公开(公告)日：2014-12-04

申请号：US14369781

申请日：2012-12-28

申请人： NEPES CO., LTD.

发明人： Yun-Mook Park ,  Byoung-Yool Jeon

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC分类号： H01L24/14 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/19 ,  H01L24/91 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/73203 ,  H01L2224/81801 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06548 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/013 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00

摘要： Disclosed herein is a semiconductor package having a fan-out structure in which a semiconductor chip is buried by an encapsulation member and an external connection member is disposed below the buried semiconductor chip. The semiconductor package includes an embedded rewiring pattern layer, an upper semiconductor chip disposed above the embedded rewiring pattern layer, an upper encapsulation member encapsulating the upper semiconductor chip, a lower semiconductor chip disposed below the embedded rewiring pattern layer, and a lower encapsulation member encapsulating the lower semiconductor chip to prevent exposure thereof.

摘要翻译： 这里公开了一种具有扇出结构的半导体封装，其中半导体芯片被封装构件掩埋，并且外部连接构件设置在掩埋半导体芯片的下方。 半导体封装包括嵌入式重新布线图案层，设置在嵌入式布线图案层上方的上半导体芯片，封装上半导体芯片的上封装件，设置在嵌入式布线图案层下方的下半导体芯片，以及封装 下半导体芯片以防止其暴露。

公开(公告)号：US20230216201A1

公开(公告)日：2023-07-06

申请号：US18145047

申请日：2022-12-22

申请人： NEPES CO., LTD.

发明人： Jung Won LEE ,  Ju Eok Park ,  In Soo Kang

IPC分类号： H01Q9/04 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L25/16 ,  H01L21/48 ,  H01L21/56 ,  H01Q1/48

CPC分类号： H01Q9/0407 ,  H01L23/49822 ,  H01L23/3128 ,  H01L23/49811 ,  H01L24/16 ,  H01L25/165 ,  H01L21/4857 ,  H01L21/563 ,  H01Q1/48 ,  H01L2224/16227 ,  H01Q1/526

摘要： A semiconductor package includes: a lower package; and an upper package stacked on the lower package, wherein the lower package includes: a first redistribution structure; a semiconductor chip mounted on the first redistribution structure; a first molding layer surrounding the semiconductor chip on the first redistribution structure; and first vertical connection conductors disposed on the first redistribution structure and vertically passing through the first molding layer, wherein the upper package includes: a second molding layer disposed on the lower package; second vertical connection conductors vertically passing through the second molding layer and electrically connected to the first vertical connection conductors; and an antenna structure disposed on the second molding layer.

公开(公告)号：US20230128862A1

公开(公告)日：2023-04-27

申请号：US17938672

申请日：2022-10-06

申请人： NEPES CO., LTD.

发明人： Yong Tae KWON ,  Hyo Young KIM ,  Eun Yeong SON ,  Seung Ho LEE ,  Kyeung Hwan KIM ,  Jong Hyun PARK

IPC分类号： H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H01L23/00 ,  H10B80/00

摘要： Provided is a semiconductor package including a redistribution structure including at least one redistribution insulating layer and at least one redistribution pattern, at least one semiconductor chip located on the redistribution structure, and a molding layer located on the redistribution structure and covering the at least one semiconductor chip. The redistribution pattern includes a redistribution via passing through the redistribution insulating layer and extending in a first direction perpendicular to a top surface of the redistribution structure, and a redistribution line extending in a second direction parallel to the top surface of the redistribution structure. Inner side walls of the redistribution via have a certain inclination, and a difference between a thickness of a central portion of the redistribution line and a thickness of an edge of the redistribution line ranges from 1% to 10% of the thickness of the central portion of the redistribution line.