公开(公告)号：US20160099210A1

公开(公告)日：2016-04-07

申请号：US14866725

申请日：2015-09-25

申请人： NEPES CO., LTD.

发明人： Yong-Tae KWON ,  Jun-Kyu LEE

IPC分类号： H01L23/522 ,  H01L25/07 ,  H01L23/528 ,  H01L21/768 ,  H01L23/532 ,  H01L23/10

CPC分类号： H01L23/528 ,  H01L21/486 ,  H01L21/568 ,  H01L21/76829 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/522 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24227 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/15311

摘要： Disclosed herein are a semiconductor package and a method of manufacturing the same, which allows a conductive path to be provided to connect upper and lower portions of the semiconductor package. A semiconductor package according to the present invention includes a semiconductor chip, a substrate including an accommodating portion to accommodate the semiconductor chip, a sealing material configured to mold the semiconductor chip and the substrate to be integrated, a through wiring configured to vertically pass through the substrate, a wiring portion configured to electrically connect the semiconductor chip and one side of the through wiring, and an external connection portion to electrically connected to the other side of the through wiring and configured to be able to be electrically connected to an outside, wherein a wiring layer of the wiring portion is provided to be connected to the through wiring.

摘要翻译： 这里公开了半导体封装及其制造方法，其允许提供导电路径以连接半导体封装的上部和下部。 根据本发明的半导体封装包括半导体芯片，包括容纳半导体芯片的容纳部分的基板，被配置为模制半导体芯片和要被集成的基板的密封材料，被配置为垂直穿过所述半导体芯片的通孔 基板，被配置为将所述半导体芯片和所述贯通布线的一侧电连接的布线部分和外部连接部分，以电连接到所述贯通布线的另一侧并且被配置为能够电连接到外部，其中 布线部分的布线层设置成连接到贯通布线。

公开(公告)号：US20190122899A1

公开(公告)日：2019-04-25

申请号：US16090602

申请日：2017-04-03

申请人： NEPES CO., LTD.

发明人： Yong-Tae KWON ,  Jun-Kyu LEE ,  Si Woo LIM ,  Dong Hoon OH ,  Jun Sung MA ,  Tae-Won KIM

IPC分类号： H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L23/525 ,  H01L23/552

摘要： A semiconductor package comprising a fan-out structure and a manufacturing method therefor are disclosed. A semiconductor package according to an embodiment of the present invention comprises: a wiring unit comprising an insulation layer and a wiring layer; a semiconductor chip mounted on the wiring unit and coupled to the wiring layer by flip-chip bonding; a filling member for filling a gap between the semiconductor chip and the wiring unit; and a film member for performing coating so as to cover one surface of each of the semiconductor chip, the filling member, and the wiring unit.

公开(公告)号：US20170069564A1

公开(公告)日：2017-03-09

申请号：US15255500

申请日：2016-09-02

申请人： NEPES CO., LTD.

发明人： Yong-Tae KWON ,  Jun-Kyu LEE

IPC分类号： H01L23/495 ,  H01L21/56 ,  H01L23/31 ,  H01L23/29 ,  H01L25/065 ,  H01L25/00

CPC分类号： H01L23/3135 ,  H01L21/486 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/9222 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06548 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/48227

摘要： Disclosed herein is a wire-bonding type semiconductor package in which a fan out metal pattern is formed and a method of manufacturing the same. The semiconductor package includes a frame configured to transfer an electrical signal between upper and lower parts and having a through part formed therein, a first semiconductor chip accommodated in the through part, a first encapsulant with which the frame and the first semiconductor chip are integrally molded, a second semiconductor chip stacked on the first semiconductor chip, a wire configured to electrically connect the second semiconductor chip to a signal unit of the frame, a second encapsulant with which the second semiconductor chip and the wire are integrally molded, and a wiring unit provided below the frame and the first semiconductor chip and electrically connected to the frame and the first semiconductor chip.

摘要翻译： 这里公开了一种其中形成扇形金属图案的引线键合型半导体封装及其制造方法。 半导体封装包括：框架，被配置为在上部和下部之间传递电信号并且具有形成在其中的通孔;容纳在通孔中的第一半导体芯片，第一密封剂，框架和第一半导体芯片通过该第一密封剂被整体模制 堆叠在第一半导体芯片上的第二半导体芯片，被配置为将第二半导体芯片电连接到框架的信号单元的导线，第二半导体芯片和导线一体地模制的第二密封剂，以及布线单元 设置在所述框架和所述第一半导体芯片的下方并且电连接到所述框架和所述第一半导体芯片。

公开(公告)号：US20160293580A1

公开(公告)日：2016-10-06

申请号：US14951434

申请日：2015-11-24

申请人： NEPES CO., LTD.

发明人： Jun-Kyu LEE ,  Yong-Tae KWON

IPC分类号： H01L25/065 ,  H01L23/495 ,  H01L23/528 ,  H01L25/00 ,  H01L21/56 ,  H01L21/311 ,  H01L23/29 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L21/31133 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49575 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/32 ,  H01L24/48 ,  H01L24/82 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/19 ,  H01L2224/2101 ,  H01L2224/215 ,  H01L2224/24011 ,  H01L2224/24175 ,  H01L2224/245 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/73277 ,  H01L2224/82106 ,  H01L2224/85005 ,  H01L2224/92 ,  H01L2224/92147 ,  H01L2224/9222 ,  H01L2224/92244 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/1441 ,  H01L2924/186 ,  H01L2924/381 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2224/83005 ,  H01L2924/014 ,  H01L2924/01029 ,  H01L2924/01013 ,  H01L2224/85 ,  H01L2224/82 ,  H01L2221/68304 ,  H01L2224/83 ,  H01L21/56 ,  H01L2221/68381 ,  H01L2924/00 ,  H01L2924/00012

摘要： Disclosed herein is a system in package and a method of manufacturing the same. The system in package includes a first semiconductor die including a plurality of bond pads, a lead frame disposed around the first semiconductor die and provided with a plurality of signal leads, a second semiconductor die disposed in an upper side of the first semiconductor die and connected to the lead frame by wire bonding, and a fan out metal pattern disposed in a lower side of the first semiconductor die and the lead frame to connect the bond pads and the signal leads electrically and provided with a plurality of metal pads.

摘要翻译： 本文公开了一种包装系统及其制造方法。 封装的系统包括：第一半导体管芯，包括多个接合焊盘;引线框架，设置在第一半导体管芯周围并设置有多个信号引线;第二半导体管芯，设置在第一半导体管芯的上侧，并连接 通过引线接合引导引线框架，以及设置在第一半导体管芯和引线框架的下侧的扇出金属图案，以将电焊点和信号引线电连接并设置有多个金属焊盘。