公开(公告)号：US20140015088A1

公开(公告)日：2014-01-16

申请号：US13934683

申请日：2013-07-03

申请人： STMicroelectronics (Crolles 2) SAS

发明人： Laurent-Luc Chapelon

IPC分类号： H01L27/04

CPC分类号： H01L27/04 ,  G01K5/56 ,  H01L22/34 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L2224/05546 ,  H01L2224/05547 ,  H01L2224/05571 ,  H01L2224/0603 ,  H01L2224/06102 ,  H01L2224/08057 ,  H01L2224/08111 ,  H01L2224/08121 ,  H01L2224/08147 ,  H01L2224/80012 ,  H01L2224/80097 ,  H01L2224/80141 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80986 ,  H01L2924/00014 ,  H01L2224/05552

摘要： A three-dimensional integrated structure is formed from a first integrated circuit with a first cavity filled with a first conductive material and a second integrated circuit with a second cavity filled with a second conductive material, the second cavity facing the first cavity. The filled first cavity forms a first element and the filled second cavity forms a second element, the first and second elements separated from each other by a cavity. The first and second conductive materials have different thermal expansion coefficients. A contact detection circuit is electrically connected to the filled first and second cavities, and is operable to sense electrical contact between the first and second conductive materials in response to a change in temperature.

摘要翻译： 三维集成结构由具有填充有第一导电材料的第一空腔的第一集成电路和具有填充有第二导电材料的第二空腔的第二集成电路形成，第二空腔面对第一空腔。 填充的第一空腔形成第一元件，并且填充的第二空腔形成第二元件，第一元件和第二元件通过空腔彼此分离。 第一和第二导电材料具有不同的热膨胀系数。 接触检测电路电连接到填充的第一和第二空腔，并且可操作以响应于温度变化来感测第一和第二导电材料之间的电接触。

公开(公告)号：US20130292823A1

公开(公告)日：2013-11-07

申请号：US13869072

申请日：2013-04-24

申请人： STMICROELECTRONICS (CROLLES 2) SAS

发明人： Laurent-Luc Chapelon

IPC分类号： H01L23/498 ,  H01L21/48

CPC分类号： H01L23/5384 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/7682 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/5386 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/80 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05647 ,  H01L2224/11912 ,  H01L2224/13005 ,  H01L2224/13007 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16237 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2224/80141 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/81141 ,  H01L2224/81815 ,  H01L2224/9201 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/2064 ,  H01L2924/20754 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2224/11 ,  H01L2224/05552 ,  H01L2924/00

摘要： A stack of a first and second semiconductor structures is formed. Each semiconductor structure includes: a semiconductor bulk, an overlying insulating layer with metal interconnection levels, and a first surface including a conductive area. The first surfaces of semiconductor structures face each other. A first interconnection pillar extends from the first surface of the first semiconductor structure. A housing opens into the first surface of the second semiconductor structure. The housing is configured to receive the first interconnection pillar. A second interconnection pillar protrudes from a second surface of the second semiconductor structure which is opposite the first surface. The second interconnection pillar is in electric contact with the first interconnection pillar.

公开(公告)号：US20150054140A1

公开(公告)日：2015-02-26

申请号：US14519832

申请日：2014-10-21

申请人： STMicroelectronics (Crolles 2) SAS

发明人： Laurent-Luc Chapelon

IPC分类号： H01L23/538 ,  H01L25/07 ,  H01L21/768 ,  H01L25/00

CPC分类号： H01L23/5384 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/7682 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/5386 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/80 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05647 ,  H01L2224/11912 ,  H01L2224/13005 ,  H01L2224/13007 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16237 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2224/80141 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/81141 ,  H01L2224/81815 ,  H01L2224/9201 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/2064 ,  H01L2924/20754 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2224/11 ,  H01L2224/05552 ,  H01L2924/00

摘要： A stack of a first and second semiconductor structures is formed. Each semiconductor structure includes: a semiconductor bulk, an overlying insulating layer with metal interconnection levels, and a first surface including a conductive area. The first surfaces of semiconductor structures face each other. A first interconnection pillar extends from the first surface of the first semiconductor structure. A housing opens into the first surface of the second semiconductor structure. The housing is configured to receive the first interconnection pillar. A second interconnection pillar protrudes from a second surface of the second semiconductor structure which is opposite the first surface. The second interconnection pillar is in electric contact with the first interconnection pillar.

摘要翻译： 形成第一和第二半导体结构的堆叠。 每个半导体结构包括：半导体本体，具有金属互连电平的上覆绝缘层，以及包括导电区域的第一表面。 半导体结构的第一表面彼此面对。 第一互连柱从第一半导体结构的第一表面延伸。 壳体通向第二半导体结构的第一表面。 壳体被配置为接收第一互连支柱。 第二互连柱从与第一表面相对的第二半导体结构的第二表面突出。 第二互连柱与第一互连柱电接触。

公开(公告)号：US08907481B2

公开(公告)日：2014-12-09

申请号：US13869072

申请日：2013-04-24

申请人： STMicroelectronics (Crolles 2) SAS

发明人： Laurent-Luc Chapelon

IPC分类号： H01L23/48 ,  H01L21/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065 ,  H01L21/683 ,  H01L21/56

CPC分类号： H01L23/5384 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/7682 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/5386 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/80 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05647 ,  H01L2224/11912 ,  H01L2224/13005 ,  H01L2224/13007 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16237 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2224/80141 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/81141 ,  H01L2224/81815 ,  H01L2224/9201 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/2064 ,  H01L2924/20754 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2224/11 ,  H01L2224/05552 ,  H01L2924/00

摘要： A stack of a first and second semiconductor structures is formed. Each semiconductor structure includes: a semiconductor bulk, an overlying insulating layer with metal interconnection levels, and a first surface including a conductive area. The first surfaces of semiconductor structures face each other. A first interconnection pillar extends from the first surface of the first semiconductor structure. A housing opens into the first surface of the second semiconductor structure. The housing is configured to receive the first interconnection pillar. A second interconnection pillar protrudes from a second surface of the second semiconductor structure which is opposite the first surface. The second interconnection pillar is in electric contact with the first interconnection pillar.

摘要翻译： 形成第一和第二半导体结构的堆叠。 每个半导体结构包括：半导体本体，具有金属互连电平的上覆绝缘层，以及包括导电区域的第一表面。 半导体结构的第一表面彼此面对。 第一互连柱从第一半导体结构的第一表面延伸。 外壳通向第二半导体结构的第一表面。 壳体被配置为接收第一互连支柱。 第二互连柱从与第一表面相对的第二半导体结构的第二表面突出。 第二互连柱与第一互连柱电接触。

公开(公告)号：US07838967B2

公开(公告)日：2010-11-23

申请号：US12108903

申请日：2008-04-24

申请人： Ming-Yao Chen

发明人： Ming-Yao Chen

IPC分类号： H01L23/488

CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L24/05 ,  H01L24/80 ,  H01L24/92 ,  H01L25/0657 ,  H01L2224/06181 ,  H01L2224/08146 ,  H01L2224/08235 ,  H01L2224/08245 ,  H01L2224/80141 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2924/00013 ,  H01L2924/01029 ,  H01L2924/15787 ,  H01L2924/351 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00

摘要： A semiconductor chip having through silicon vias (TSV) and a stacked assembly including the chip are revealed. The chip has a plurality of first and second bonding pads disposed on two opposing surfaces of a semiconductor substrate respectively. Through hole vertically penetrate through the semiconductor substrate and the first and second bonding pads. By forming first extruded ring, the first bonding pad has a first contact surface located between the first extruded ring and the through hole. By forming second extruded ring, the second bonding pad has a second contact surface located outside and adjacent to the second extruded rings to encircle the second extruded ring. The second extruded ring has a proper dimension to fit in the first extruded ring. Accordingly, a plurality of semiconductor chip can be stacked each other with accurate alignment without shifting to effectively reduce the stacked assembly height, moreover, chip stacking processes are accomplished by vertically stacking a plurality of chips first then filling conductive material into the through holes without electrical short between the adjacent bonding pads due to overflow of conductive material to meet the fine-pitch requirements of TSV. The process flow for the stacked assembly is simplified with higher production yields.

摘要翻译： 揭示了通过硅通孔（TSV）的半导体芯片和包括芯片的堆叠组件。 芯片具有分别设置在半导体衬底的两个相对表面上的多个第一和第二接合焊盘。 通孔垂直地穿过半导体衬底和第一和第二焊盘。 通过形成第一挤压环，第一接合焊盘具有位于第一挤压环和通孔之间的第一接触表面。 通过形成第二挤压环，第二接合焊盘具有位于第二挤压环的外侧并与第二挤压环相邻的第二接触表面，以环绕第二挤压环。 第二挤压环具有适合尺寸以适合第一挤出环。 因此，可以精确地对准多个半导体芯片，而不需要移位，从而有效地降低堆叠的组装高度，此外，首先通过垂直堆叠多个芯片，然后将导电材料填充到通孔中而不用电 由于导电材料溢出而导致相邻焊盘之间短路，以满足TSV的精细间距要求。 叠层组件的工艺流程可以通过更高的生产率得到简化。

公开(公告)号：US20090267194A1

公开(公告)日：2009-10-29

申请号：US12108903

申请日：2008-04-24

申请人： Ming-Yao CHEN

发明人： Ming-Yao CHEN

IPC分类号： H01L23/488

CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L24/05 ,  H01L24/80 ,  H01L24/92 ,  H01L25/0657 ,  H01L2224/06181 ,  H01L2224/08146 ,  H01L2224/08235 ,  H01L2224/08245 ,  H01L2224/80141 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2924/00013 ,  H01L2924/01029 ,  H01L2924/15787 ,  H01L2924/351 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00

摘要： A semiconductor chip having through silicon vias (TSV) and a stacked assembly including the chip are revealed. The chip has a plurality of first and second bonding pads disposed on two opposing surfaces of a semiconductor substrate respectively. Through hole vertically penetrate through the semiconductor substrate and the first and second bonding pads. By forming first extruded ring, the first bonding pad has a first contact surface located between the first extruded ring and the through hole. By forming second extruded ring, the second bonding pad has a second contact surface located outside and adjacent to the second extruded rings to encircle the second extruded ring. The second extruded ring has a proper dimension to fit in the first extruded ring. Accordingly, a plurality of semiconductor chip can be stacked each other with accurate alignment without shifting to effectively reduce the stacked assembly height, moreover, chip stacking processes are accomplished by vertically stacking a plurality of chips first then filling conductive material into the through holes without electrical short between the adjacent bonding pads due to overflow of conductive material to meet the fine-pitch requirements of TSV. The process flow for the stacked assembly is simplified with higher production yields.

摘要翻译： 揭示了通过硅通孔（TSV）的半导体芯片和包括芯片的堆叠组件。 芯片具有分别设置在半导体衬底的两个相对表面上的多个第一和第二接合焊盘。 通孔垂直地穿过半导体衬底和第一和第二焊盘。 通过形成第一挤压环，第一接合焊盘具有位于第一挤压环和通孔之间的第一接触表面。 通过形成第二挤压环，第二接合焊盘具有位于第二挤压环的外侧并与第二挤压环相邻的第二接触表面，以环绕第二挤压环。 第二挤压环具有适合尺寸以适合第一挤出环。 因此，可以精确地对准多个半导体芯片，而不需要移位，从而有效地降低堆叠的组装高度，此外，首先通过垂直堆叠多个芯片，然后将导电材料填充到通孔中而不用电 由于导电材料溢出而导致相邻焊盘之间短路，以满足TSV的精细间距要求。 叠层组件的工艺流程可以通过更高的生产率得到简化。

公开(公告)号：US09093456B2

公开(公告)日：2015-07-28

申请号：US14519832

申请日：2014-10-21

申请人： STMicroelectronics (Crolles 2) SAS

发明人： Laurent-Luc Chapelon

IPC分类号： H01L21/48 ,  H01L21/768 ,  H01L23/498 ,  H01L25/065 ,  H01L23/538 ,  H01L23/48 ,  H01L25/00 ,  H01L25/07 ,  H01L21/56 ,  H01L23/00 ,  H01L21/683

CPC分类号： H01L23/5384 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/7682 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/5386 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/80 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05647 ,  H01L2224/11912 ,  H01L2224/13005 ,  H01L2224/13007 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16237 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2224/80141 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/81141 ,  H01L2224/81815 ,  H01L2224/9201 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/2064 ,  H01L2924/20754 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2224/11 ,  H01L2224/05552 ,  H01L2924/00

摘要： A stack of a first and second semiconductor structures is formed. Each semiconductor structure includes: a semiconductor bulk, an overlying insulating layer with metal interconnection levels, and a first surface including a conductive area. The first surfaces of semiconductor structures face each other. A first interconnection pillar extends from the first surface of the first semiconductor structure. A housing opens into the first surface of the second semiconductor structure. The housing is configured to receive the first interconnection pillar. A second interconnection pillar protrudes from a second surface of the second semiconductor structure which is opposite the first surface. The second interconnection pillar is in electric contact with the first interconnection pillar.

摘要翻译： 形成第一和第二半导体结构的堆叠。 每个半导体结构包括：半导体本体，具有金属互连电平的上覆绝缘层，以及包括导电区域的第一表面。 半导体结构的第一表面彼此面对。 第一互连柱从第一半导体结构的第一表面延伸。 壳体通向第二半导体结构的第一表面。 壳体被配置为接收第一互连支柱。 第二互连柱从与第一表面相对的第二半导体结构的第二表面突出。 第二互连柱与第一互连柱电接触。

公开(公告)号：US08890276B2

公开(公告)日：2014-11-18

申请号：US13934683

申请日：2013-07-03

申请人： STMicroelectronics (Crolles 2) SAS

发明人： Laurent-Luc Chapelon

IPC分类号： H01L31/058 ,  H01L27/04 ,  H01L21/66 ,  G01K5/56 ,  H01L23/00

CPC分类号： H01L27/04 ,  G01K5/56 ,  H01L22/34 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L2224/05546 ,  H01L2224/05547 ,  H01L2224/05571 ,  H01L2224/0603 ,  H01L2224/06102 ,  H01L2224/08057 ,  H01L2224/08111 ,  H01L2224/08121 ,  H01L2224/08147 ,  H01L2224/80012 ,  H01L2224/80097 ,  H01L2224/80141 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80986 ,  H01L2924/00014 ,  H01L2224/05552

摘要： A three-dimensional integrated structure is formed from a first integrated circuit with a first cavity filled with a first conductive material and a second integrated circuit with a second cavity filled with a second conductive material, the second cavity facing the first cavity. The filled first cavity forms a first element and the filled second cavity forms a second element, the first and second elements separated from each other by a cavity. The first and second conductive materials have different thermal expansion coefficients. A contact detection circuit is electrically connected to the filled first and second cavities, and is operable to sense electrical contact between the first and second conductive materials in response to a change in temperature.

摘要翻译： 三维集成结构由具有填充有第一导电材料的第一空腔的第一集成电路和具有填充有第二导电材料的第二空腔的第二集成电路形成，第二空腔面对第一空腔。 填充的第一空腔形成第一元件，并且填充的第二空腔形成第二元件，第一元件和第二元件通过空腔彼此分离。 第一和第二导电材料具有不同的热膨胀系数。 接触检测电路电连接到填充的第一和第二空腔，并且可操作以响应于温度变化来感测第一和第二导电材料之间的电接触。

公开(公告)号：US20140090234A1

公开(公告)日：2014-04-03

申请号：US14119575

申请日：2012-05-23

申请人： David Kazmer

发明人： David Kazmer

IPC分类号： H01L23/544

CPC分类号： H01L23/544 ,  H01L23/3128 ,  H01L24/75 ,  H01L24/81 ,  H01L2223/54426 ,  H01L2224/75315 ,  H01L2224/80141 ,  H01L2224/81141 ,  H01L2924/12042 ,  Y10T29/5313 ,  Y10T29/53261 ,  H01L2924/00

摘要： Apparatus and methods for self-alignment and assembly of objects with micron-level and/or nanometer-level alignment accuracy. Mating alignment features spanning multiple length scales are disposed at surfaces of objects to be brought into contact. When the objects are pressed together, the alignment features guide alignment of the objects with respect to each other. The alignment features may provide retaining forces to hold the objects together. Micron-level and nanometer-level alignment accuracies may be achieved over large surface areas.

摘要翻译： 用于自对准和组装具有微米级和/或纳米级对准精度的物体的装置和方法。 跨越多个长度尺度的配合对准特征设置在要接触的物体的表面。 当对象被按压在一起时，对准特征引导对象相对于彼此的对准。 对准特征可以提供保持力以将物体保持在一起。 可以在大的表面积上实现微米级和纳米级对准精度。

公开(公告)号：US5753536A

公开(公告)日：1998-05-19

申请号：US520252

申请日：1995-08-28

申请人： Tatsuo Sugiyama ,  Shuji Hirao ,  Kousaku Yano ,  Noboru Nomura

发明人： Tatsuo Sugiyama ,  Shuji Hirao ,  Kousaku Yano ,  Noboru Nomura

IPC分类号： H01L21/98 ,  H01L25/065 ,  H01L21/60

CPC分类号： H01L23/544 ,  H01L21/76898 ,  H01L24/05 ,  H01L24/12 ,  H01L24/16 ,  H01L24/80 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/54426 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/08145 ,  H01L2224/13099 ,  H01L2224/80141 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/81121 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2224/83894 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06593 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3511

摘要： A first electrode and a first insulating layer of electrode insulation are formed on a first semiconductor substrate. A second electrode and a second insulating layer of electrode insulation are formed on a second semiconductor substrate. The first semiconductor substrate has at its surface a pattern of recesses/projections (i.e., a pattern of sawteeth in cross section) at regular intervals in stripe arrangement. Likewise, the second semiconductor substrate has at its surface a pattern of recesses/projections (i.e., a pattern of sawteeth in cross section) at regular intervals in stripe arrangement, wherein the pattern of the second semiconductor substrate has a phase shift of 180 degrees with respect to the pattern of the first semiconductor substrate. The first and second semiconductor substrates are bonded together with their patterns in engagement.

摘要翻译： 在第一半导体衬底上形成有电极绝缘体的第一电极和第一绝缘层。 在第二半导体衬底上形成第二电极和电极绝缘的第二绝缘层。 第一半导体衬底在其表面上以条纹布置的规则间隔在其表面处具有凹槽/突起的图案（即横截面的锯齿形图案）。 类似地，第二半导体衬底在其表面上在条纹布置中以规则的间隔在其表面处具有凹槽/突起的图案（即，横截面的锯齿形图案），其中第二半导体衬底的图案具有180度的相移， 相对于第一半导体衬底的图案。 第一和第二半导体衬底以它们的图案接合在一起。