公开(公告)号：US20210265168A1

公开(公告)日：2021-08-26

申请号：US17315943

申请日：2021-05-10

Applicant: Infineon Technologies AG

Inventor： Stefan Krivec ,  Ronny Kern ,  Stefan Kramp ,  Gregor Langer ,  Hannes Winkler ,  Stefan Woehlert

IPC: H01L21/04 ,  H01L29/16 ,  H01L29/45 ,  H01L21/02

Abstract: A process for producing an electrical contact with a first metal layer and at least one second metal layer on a silicon carbide substrate includes removing at least some of the carbon residue by a cleaning process, to clean the first metal layer. The first metal layer and/or the at least one second metal layer may be generated by sputtering deposition.

公开(公告)号：US20170033067A1

公开(公告)日：2017-02-02

申请号：US14809296

申请日：2015-07-27

Applicant: Infineon Technologies AG

Inventor： Stefan Kramp

IPC: H01L23/00 ,  H01L21/768

CPC classification number: H01L24/06 ,  H01L21/76832 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/27 ,  H01L24/29 ,  H01L24/45 ,  H01L24/73 ,  H01L2224/0345 ,  H01L2224/03614 ,  H01L2224/0381 ,  H01L2224/03901 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05583 ,  H01L2224/05611 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/06505 ,  H01L2224/1131 ,  H01L2224/11332 ,  H01L2224/11849 ,  H01L2224/13023 ,  H01L2224/13118 ,  H01L2224/13123 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16245 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45157 ,  H01L2224/48245 ,  H01L2224/48491 ,  H01L2224/73207 ,  H01L2224/8181 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/0361 ,  H01L2924/01074

Abstract: According to various embodiments, a semiconductor device may include: at least one first contact pad on a front side of the semiconductor device; at least one second contact pad on the front side of the semiconductor device; a layer stack disposed at least partially over the at least one first contact pad, wherein the at least one second contact pad is at least partially free of the layer stack; wherein the layer stack includes at least an adhesion layer and a metallization layer; and wherein the metallization layer includes a metal alloy and wherein the adhesion layer is disposed between the metallization layer and the at least one first contact pad for adhering the metal alloy of the metallization layer to the at least one first contact pad.

Abstract translation: 根据各种实施例，半导体器件可以包括：在半导体器件的正面上的至少一个第一接触焊盘; 在所述半导体器件的正面上的至少一个第二接触焊盘; 至少部分地布置在所述至少一个第一接触垫上的层堆叠，其中所述至少一个第二接触焊盘至少部分地不含所述层堆叠; 其中所述层堆叠至少包括粘附层和金属化层; 并且其中所述金属化层包括金属合金，并且其中所述粘合层设置在所述金属化层和所述至少一个第一接触焊盘之间，用于将所述金属化层的所述金属合金粘附到所述至少一个第一接触焊盘。

公开(公告)号：US20130252382A1

公开(公告)日：2013-09-26

申请号：US13893937

申请日：2013-05-14

Applicant: Infineon Technologies AG

Inventor： Oliver Haeberlen ,  Klaus Schiess ,  Stefan Kramp

IPC: H01L21/50

CPC classification number: H01L23/49861 ,  H01L21/561 ,  H01L23/142 ,  H01L23/3121 ,  H01L23/315 ,  H01L23/3157 ,  H01L23/3171 ,  H01L23/3185 ,  H01L23/36 ,  H01L23/492 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49575 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/82 ,  H01L24/97 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05572 ,  H01L2224/05639 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/13099 ,  H01L2224/24226 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2224/82 ,  H01L2224/83 ,  H01L2224/19 ,  H01L2924/00 ,  H01L2224/05099

Abstract: A method of manufacturing a semiconductor device includes providing an electrically conductive carrier and placing a semiconductor chip over the carrier. The method includes applying an electrically insulating layer over the carrier and the semiconductor chip. The electrically insulating layer has a first face facing the carrier and a second face opposite to the first face. The method includes selectively removing the electrically insulating layer and applying solder material where the electrically insulating layer is removed and on the second face of the electrically insulating layer.

Abstract translation: 制造半导体器件的方法包括提供导电载体并将半导体芯片放置在载体上。 该方法包括在载体和半导体芯片上施加电绝缘层。 电绝缘层具有面向载体的第一面和与第一面相对的第二面。 该方法包括选择性地去除电绝缘层并施加去除电绝缘层并且在电绝缘层的第二面上的焊料材料。

公开(公告)号：US11798807B2

公开(公告)日：2023-10-24

申请号：US17315943

申请日：2021-05-10

Applicant: Infineon Technologies AG

Inventor： Stefan Krivec ,  Ronny Kern ,  Stefan Kramp ,  Gregor Langer ,  Hannes Winkler ,  Stefan Woehlert

IPC: H01L21/04 ,  H01L29/16 ,  H01L29/45 ,  H01L21/02

CPC classification number: H01L21/0485 ,  H01L21/02068 ,  H01L29/1608 ,  H01L29/45

Abstract: A process for producing an electrical contact with a first metal layer and at least one second metal layer on a silicon carbide substrate includes removing at least some of the carbon residue by a cleaning process, to clean the first metal layer. The first metal layer and/or the at least one second metal layer may be generated by sputtering deposition.

公开(公告)号：US11217500B2

公开(公告)日：2022-01-04

申请号：US16379289

申请日：2019-04-09

Applicant: Infineon Technologies AG

Inventor： Jens Peter Konrath ,  Wolfgang Bergner ,  Romain Esteve ,  Richard Gaisberger ,  Florian Grasse ,  Jochen Hilsenbeck ,  Ravi Keshav Joshi ,  Stefan Kramp ,  Stefan Krivec ,  Grzegorz Lupina ,  Hiroshi Narahashi ,  Andreas Voerckel ,  Stefan Woehlert

IPC: H01L23/31 ,  H01L23/29 ,  H01L21/56 ,  H01L29/16 ,  H01L29/861 ,  H01L29/78 ,  H01L21/768 ,  H01L23/532

Abstract: A semiconductor device includes a contact metallization layer arranged on a semiconductor substrate, an inorganic passivation structure arranged on the semiconductor substrate, and an organic passivation layer. The organic passivation layer is located between the contact metallization layer and the inorganic passivation structure, and located vertically closer to the semiconductor substrate than a part of the organic passivation layer located on top of the inorganic passivation structure.

公开(公告)号：US09435849B2

公开(公告)日：2016-09-06

申请号：US14319268

申请日：2014-06-30

Applicant: Infineon Technologies AG

Inventor： Erwin Thalmann ,  Michael Leutschacher ,  Christian Musshoff ,  Stefan Kramp

IPC: G01R31/26 ,  G01R1/073

CPC classification number: G01R31/2608 ,  G01R1/07342 ,  G01R31/2601 ,  G01R31/2621 ,  G01R31/2637 ,  G01R31/2644

Abstract: A method includes: providing a test apparatus; providing an electrically conductive carrier; providing a semiconductor substrate having a first main face, a second main face opposite to the first main face, and a plurality of semiconductor dies, the semiconductor dies including a first contact element on the first main face and a second contact element on the second main face; placing the semiconductor substrate on the carrier with the second main face facing the carrier; electrically connecting the carrier to a contact location disposed on the first main face; and testing a semiconductor die by electrically connecting the test apparatus with the first contact element of the semiconductor die and the contact location.

Abstract translation: 一种方法包括：提供测试装置; 提供导电载体; 提供具有第一主面，与第一主面相反的第二主面的半导体衬底和多个半导体管芯，所述半导体管芯包括在第一主面上的第一接触元件和第二主体上的第二接触元件 面对; 将所述半导体衬底放置在所述载体上，其中所述第二主面朝向所述载体; 将所述载体电连接到设置在所述第一主面上的接触位置; 以及通过将测试装置与半导体管芯的第一接触元件和接触位置电连接来测试半导体管芯。

公开(公告)号：US20230420257A1

公开(公告)日：2023-12-28

申请号：US18240520

申请日：2023-08-31

Applicant: Infineon Technologies AG

Inventor： Stefan Krivec ,  Ronny Kern ,  Stefan Kramp ,  Gregor Langer ,  Hannes Winkler ,  Stefan Woehlert

IPC: H01L21/04 ,  H01L29/16 ,  H01L29/45 ,  H01L21/02

CPC classification number: H01L21/0485 ,  H01L29/1608 ,  H01L29/45 ,  H01L21/02068

Abstract: A chip is provided. In an embodiment, the chip includes a silicon carbide substrate, a first sputtered metal layer on the silicon carbide substrate, and at least one second sputtered metal layer on the first sputtered metal layer. The first sputtered metal layer and the at least one second sputtered metal layer form an electrical contact. In another embodiment, the chip includes a silicon carbide substrate, a nickel-silicon layer on the silicon carbide substrate, and a layer sequence including a titanium layer, a nickel-containing layer, and a gold-tin or silver layer on the nickel-silicon layer.

公开(公告)号：US11842938B2

公开(公告)日：2023-12-12

申请号：US17538162

申请日：2021-11-30

Applicant: Infineon Technologies AG

Inventor： Jens Peter Konrath ,  Wolfgang Bergner ,  Romain Esteve ,  Richard Gaisberger ,  Florian Grasse ,  Jochen Hilsenbeck ,  Ravi Keshav Joshi ,  Stefan Kramp ,  Stefan Krivec ,  Grzegorz Lupina ,  Hiroshi Narahashi ,  Andreas Voerckel ,  Stefan Woehlert

IPC: H01L23/31 ,  H01L23/29 ,  H01L21/56 ,  H01L29/16 ,  H01L29/861 ,  H01L29/78 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/3192 ,  H01L21/56 ,  H01L21/76841 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3171 ,  H01L23/53223 ,  H01L29/1608 ,  H01L29/7811 ,  H01L29/8611

Abstract: A semiconductor device includes a contact metallization layer that includes aluminum and is arranged on a semiconductor substrate, an inorganic passivation structure arranged on the semiconductor substrate, an organic passivation layer comprising a first part that is arranged on the contact metallization layer, and a second part that is arranged on the inorganic passivation structure, a first layer structure including a first part that is in contact with the contact metallization layer, a second part that is contact with the inorganic passivation structure, and a third part that is disposed on the semiconductor substrate laterally between the inorganic passivation structure and the organic passivation layer.

公开(公告)号：US20220093483A1

公开(公告)日：2022-03-24

申请号：US17538162

申请日：2021-11-30

Applicant: Infineon Technologies AG

Inventor： Jens Peter Konrath ,  Wolfgang Bergner ,  Romain Esteve ,  Richard Gaisberger ,  Florian Grasse ,  Jochen Hilsenbeck ,  Ravi Keshav Joshi ,  Stefan Kramp ,  Stefan Krivec ,  Grzegorz Lupina ,  Hiroshi Narahashi ,  Andreas Voerckel ,  Stefan Woehlert

IPC: H01L23/31 ,  H01L23/29 ,  H01L21/56 ,  H01L29/16 ,  H01L29/861 ,  H01L29/78 ,  H01L21/768 ,  H01L23/532

Abstract: A semiconductor device includes a contact metallization layer that includes aluminum and is arranged on a semiconductor substrate, an inorganic passivation structure arranged on the semiconductor substrate, an organic passivation layer comprising a first part that is arranged on the contact metallization layer, and a second part that is arranged on the inorganic passivation structure, a first layer structure including a first part that is in contact with the contact metallization layer, a second part that is contact with the inorganic passivation structure, and a third part that is disposed on the semiconductor substrate laterally between the inorganic passivation structure and the organic passivation layer.

公开(公告)号：US11043383B2

公开(公告)日：2021-06-22

申请号：US16422373

申请日：2019-05-24

Applicant: Infineon Technologies AG

Inventor： Stefan Krivec ,  Ronny Kern ,  Stefan Kramp ,  Gregor Langer ,  Hannes Winkler ,  Stefan Woehlert

IPC: H01L21/04 ,  H01L29/16 ,  H01L29/45 ,  H01L21/02

Abstract: A process for producing an electrical contact with a first metal layer and at least one second metal layer on a silicon carbide substrate includes removing at least some of the carbon residue by a chemical cleaning process, to clean the first metal layer. The first metal layer and/or the at least one second metal layer may be generated by sputtering deposition.