公开(公告)号：US20230395663A1

公开(公告)日：2023-12-07

申请号：US18317542

申请日：2023-05-15

Applicant: Infineon Technologies AG

Inventor： Thomas Ralf Siemieniec ,  Wolfgang Bergner

IPC: H01L29/08 ,  H01L29/417 ,  H01L29/78 ,  H01L29/16 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/0852 ,  H01L29/41741 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/4236 ,  H01L21/0485

Abstract: A semiconductor component includes: gate structures extending into a silicon carbide body from a first surface and having a width along a first horizontal direction parallel to the first surface that is less than a vertical extent of the gate structures perpendicular to the first surface; contact structures extending into the silicon carbide body from the first surface, the gate and contact structures alternating along the first horizontal direction; shielding regions which, in the silicon carbide body, adjoin a bottom of the contact structures and are spaced apart from the gate structures along the first horizontal direction; and source regions between the first surface and body regions. The body regions form pn junctions with the source regions and include main sections adjoining the gate structures and contact sections adjoining the contact structures. A vertical extent of the contact structures is greater than the vertical extent of the gate structures.

公开(公告)号：US11217500B2

公开(公告)日：2022-01-04

申请号：US16379289

申请日：2019-04-09

Applicant: Infineon Technologies AG

Inventor： Jens Peter Konrath ,  Wolfgang Bergner ,  Romain Esteve ,  Richard Gaisberger ,  Florian Grasse ,  Jochen Hilsenbeck ,  Ravi Keshav Joshi ,  Stefan Kramp ,  Stefan Krivec ,  Grzegorz Lupina ,  Hiroshi Narahashi ,  Andreas Voerckel ,  Stefan Woehlert

IPC: H01L23/31 ,  H01L23/29 ,  H01L21/56 ,  H01L29/16 ,  H01L29/861 ,  H01L29/78 ,  H01L21/768 ,  H01L23/532

Abstract: A semiconductor device includes a contact metallization layer arranged on a semiconductor substrate, an inorganic passivation structure arranged on the semiconductor substrate, and an organic passivation layer. The organic passivation layer is located between the contact metallization layer and the inorganic passivation structure, and located vertically closer to the semiconductor substrate than a part of the organic passivation layer located on top of the inorganic passivation structure.

公开(公告)号：US20210343835A1

公开(公告)日：2021-11-04

申请号：US17375034

申请日：2021-07-14

Applicant: Infineon Technologies AG

Inventor： Ralf Siemieniec ,  Thomas Aichinger ,  Thomas Basler ,  Wolfgang Bergner ,  Rudolf Elpelt ,  Romain Esteve ,  Michael Hell ,  Daniel Kueck ,  Caspar Leendertz ,  Dethard Peters ,  Hans-Joachim Schulze

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/16 ,  H01L21/04 ,  H01L29/66 ,  H01L29/10

Abstract: A semiconductor component includes: gate structures extending from a first surface into an SiC semiconductor body; a drift zone of a first conductivity type formed in the SiC semiconductor body; first mesas and second mesas arranged between the gate structures in the SiC semiconductor body; body areas of a second conductivity type arranged in the first mesas and the second mesas, the body areas each adjoining a first side wall of one of the gate structures; first shielding areas of the second conductivity type adjoining a second side wall of one of the gate structures; second shielding areas of the second conductivity type adjoining the body areas in the second mesas; and diode areas of the conductivity type of the drift zone, the diode areas forming Schottky contacts with a load electrode between the first shielding areas and the second shielding areas.

公开(公告)号：US11063142B2

公开(公告)日：2021-07-13

申请号：US16721088

申请日：2019-12-19

Applicant: Infineon Technologies AG

Inventor： Jens Peter Konrath ,  Wolfgang Bergner ,  Christian Hecht ,  Hans-Joachim Schulze ,  Andre Rainer Stegner

IPC: H01L29/739 ,  H01L29/16 ,  H01L29/32 ,  H01L29/40 ,  H01L29/66 ,  H01L21/04 ,  H01L29/47

Abstract: A semiconductor device includes a silicon carbide body that includes a first section and a second section. The first section is adjacent to the second section. A drift region is formed in the first section and the second section. A lattice defect region is in a portion of the drift region in the second section. A first density of lattice defects, which include interstitials and vacancies in the lattice defect region, is at least double a second density of lattice defects, which include interstitials and vacancies in a portion of the drift region outside the lattice defect region.

公开(公告)号：US10886370B2

公开(公告)日：2021-01-05

申请号：US16669742

申请日：2019-10-31

Applicant: Infineon Technologies AG

Inventor： Florian Grasse ,  Axel Sascha Baier ,  Wolfgang Bergner ,  Barbara Englert ,  Christian Strenger

IPC: H01L29/10 ,  H01L29/16 ,  H01L29/08 ,  H01L21/04 ,  H01L29/78

Abstract: A silicon carbide body includes a drift structure having a first conductivity type, a body region, and a shielding region. The body and shielding regions, of a second conductivity type, are located between the drift structure and a first surface of the silicon carbide body. First and second trench gate stripes extend into the silicon carbide body. The body region is in contact with a first sidewall of the first trench gate stripe. The shielding region is in contact with a second sidewall of the second trench gate stripe. The second sidewall has a first length in a lateral first direction parallel to the first surface. A supplementary region of the first conductivity type contacts one or more interface areas of the second sidewall. The one or more interface areas have a combined second length along the first direction, the second length being at most 40% of the first length.

公开(公告)号：US10211306B2

公开(公告)日：2019-02-19

申请号：US15866755

申请日：2018-01-10

Applicant: Infineon Technologies AG

Inventor： Ralf Siemieniec ,  Dethard Peters ,  Romain Esteve ,  Wolfgang Bergner ,  Thomas Aichinger ,  Daniel Kueck ,  Roland Rupp ,  Bernd Zippelius ,  Karlheinz Feldrapp ,  Christian Strenger

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L29/739 ,  H01L29/04 ,  H01L29/423 ,  H01L29/40 ,  H01L29/16 ,  H01L29/20

Abstract: A semiconductor device includes a semiconductor body formed from a semiconductor material with a band-gap of at least 2.0 eV, the semiconductor body having a diode region and a source region. The semiconductor device further includes a trench gate structure having a first sidewall and a second sidewall opposite the first sidewall, the first sidewall and the second sidewall extending along a common longitudinal direction. A doping concentration of a first doping type is higher in the diode region than in the source region. The trench gate structure projects from a first surface of the semiconductor body into the semiconductor body. A first portion of the second sidewall at the first surface is directly adjoined by the source region. A second portion of the second sidewall is in direct contact with the diode region. Additional semiconductor device embodiments are provided.

公开(公告)号：US09934972B2

公开(公告)日：2018-04-03

申请号：US15288349

申请日：2016-10-07

Applicant: Infineon Technologies AG

Inventor： Thomas Aichinger ,  Wolfgang Bergner ,  Romain Esteve ,  Daniel Kueck ,  Dethard Peters ,  Victorina Poenariu ,  Gerald Reinwald ,  Roland Rupp ,  Gerald Unegg

IPC: H01L21/04 ,  H01L21/02 ,  H01L21/265 ,  H01L29/78 ,  H01L29/66 ,  H01L29/16 ,  H01L29/10 ,  H01L29/40 ,  H01L29/861 ,  H01L29/06 ,  H01L21/3065 ,  H01L29/423

CPC classification number: H01L21/0475 ,  H01L21/049 ,  H01L21/3065 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/401 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66068 ,  H01L29/7813 ,  H01L29/8613

Abstract: A trench is formed that extends from a main surface into a crystalline silicon carbide semiconductor layer. A mask is formed that includes a mask opening exposing the trench and a rim section of the main surface around the trench. By irradiation with a particle beam a first portion of the semiconductor layer exposed by the mask opening and a second portion outside of the vertical projection of the mask opening and directly adjoining to the first portion are amorphized. A vertical extension of the amorphized second portion gradually decreases with increasing distance to the first portion. The amorphized first and second portions are removed.

公开(公告)号：US09478655B2

公开(公告)日：2016-10-25

申请号：US14718443

申请日：2015-05-21

Applicant: Infineon Technologies AG

Inventor： Ralf Siemieniec ,  Wolfgang Bergner ,  Romain Esteve ,  Dethard Peters

IPC: H01L29/15 ,  H01L31/0312 ,  H01L29/78 ,  H01L29/16 ,  H01L29/66 ,  H01L29/167 ,  H01L21/04 ,  H01L29/423 ,  H01L29/04 ,  H01L29/861 ,  H01L29/06

CPC classification number: H01L29/7805 ,  H01L21/046 ,  H01L29/045 ,  H01L29/0688 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/167 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/66734 ,  H01L29/78 ,  H01L29/7804 ,  H01L29/7813 ,  H01L29/861

Abstract: A semiconductor device includes a semiconductor body and at least one device cell integrated in the semiconductor body. Each device cell includes: a drift region, a source region, and a body region arranged between the source and drift regions; a diode region and a pn junction between the diode and drift regions; a trench having a first sidewall, a second sidewall opposite the first sidewall, and a bottom, the body region adjoining the first sidewall, the diode region adjoining the second sidewall, and the pn junction adjoining the bottom; a gate electrode in the trench and dielectrically insulated from the body, diode and drift regions by a gate dielectric. The diode region has a lower diode region arranged below the trench bottom, and the lower diode region has a maximum of a doping concentration distant to the trench bottom. A corresponding method of manufacturing the device also is provided.

Abstract translation: 半导体器件包括半导体本体和集成在半导体本体中的至少一个器件单元。 每个器件单元包括：漂移区，源区和布置在源极和漂移区之间的体区; 二极管区域和二极管与漂移区域之间的pn结; 具有第一侧壁，与第一侧壁相对的第二侧壁和底部，与第一侧壁邻接的主体区域，邻接第二侧壁的二极管区域和与底部相邻的pn结的沟槽; 沟槽中的栅极，并通过栅极电介质与体，二极管和漂移区介电绝缘。 二极管区域具有布置在沟槽底部下方的较低二极管区域，并且下二极管区域具有远离沟槽底部的掺杂浓度的最大值。 还提供了相应的制造装置的方法。

公开(公告)号：US20160181408A1

公开(公告)日：2016-06-23

申请号：US14976566

申请日：2015-12-21

Applicant: Infineon Technologies AG

Inventor： Thomas Aichinger ,  Wolfgang Bergner

IPC: H01L29/739 ,  H01L29/423 ,  H01L29/06 ,  H01L29/16

CPC classification number: H01L29/4236 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/049 ,  H01L21/823462 ,  H01L24/48 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/7397 ,  H01L29/7813 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/45099

Abstract: A semiconductor device includes a transistor cell with a stripe-shaped trench gate structure that extends from a first surface into a semiconductor body. A gate connector structure at a distance to the first surface is electrically connected to a gate electrode in the trench gate structure. A gate dielectric separates the gate electrode from the semiconductor body. First sections of the gate dielectric outside a vertical projection of the gate connector structure are thinner than second sections within the vertical projection of the gate connector structure.

Abstract translation: 半导体器件包括具有从第一表面延伸到半导体本体的条形沟槽栅极结构的晶体管单元。 距离第一表面一定距离的栅极连接器结构电连接到沟槽栅极结构中的栅电极。 栅极电介质将栅电极与半导体本体分开。 栅极连接器结构的垂直投影外部的栅极电介质的第一部分比栅极连接器结构的垂直投影内的第​​二部分薄。

公开(公告)号：US20160172468A1

公开(公告)日：2016-06-16

申请号：US14567504

申请日：2014-12-11

Applicant: Infineon Technologies AG

Inventor： Romain Esteve ,  Dethard Peters ,  Wolfgang Bergner ,  Ralf Siemieniec ,  Thomas Aichinger ,  Daniel Kueck

IPC: H01L29/66 ,  H01L29/423 ,  H01L21/311 ,  H01L21/324 ,  H01L21/04 ,  H01L29/16 ,  H01L21/02

CPC classification number: H01L29/063 ,  H01L21/02236 ,  H01L21/045 ,  H01L21/0465 ,  H01L21/0475 ,  H01L21/049 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/324 ,  H01L21/3247 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/66068 ,  H01L29/66734 ,  H01L29/7813

Abstract: A silicon-carbide semiconductor substrate having a plurality of first doped regions being laterally spaced apart from one another and beneath a main surface, and a second doped region extending from the main surface to a third doped region that is above the first doped regions is formed. Fourth doped regions extending from the main surface to the first doped regions are formed. A gate trench having a bottom that is arranged over a portion of one of the first doped regions is formed. A high-temperature step is applied to the substrate so as to realign silicon-carbide atoms along sidewalls of the trench and form rounded corners in the gate trench. A surface layer that forms along the sidewalls of the gate trench during the high-temperature step from the substrate is removed.

Abstract translation: 一种碳化硅半导体衬底，其具有多个第一掺杂区域，该第一掺杂区域在主表面之间彼此横向间隔开，并且形成从主表面延伸至位于第一掺杂区域之上的第三掺杂区域的第二掺杂区域 。 形成从主表面延伸到第一掺杂区的第四掺杂区。 形成具有布置在一个第一掺杂区域的一部分上的底部的栅极沟槽。 将高温步骤施加到衬底上，以便沿着沟槽的侧壁重新排列碳化硅原子，并在栅极沟槽中形成圆角。 去除在离开衬底的高温步骤期间沿着栅极沟槽的侧壁形成的表面层。