公开(公告)号：US11217500B2

公开(公告)日：2022-01-04

申请号：US16379289

申请日：2019-04-09

Applicant: Infineon Technologies AG

Inventor： Jens Peter Konrath ,  Wolfgang Bergner ,  Romain Esteve ,  Richard Gaisberger ,  Florian Grasse ,  Jochen Hilsenbeck ,  Ravi Keshav Joshi ,  Stefan Kramp ,  Stefan Krivec ,  Grzegorz Lupina ,  Hiroshi Narahashi ,  Andreas Voerckel ,  Stefan Woehlert

IPC: H01L23/31 ,  H01L23/29 ,  H01L21/56 ,  H01L29/16 ,  H01L29/861 ,  H01L29/78 ,  H01L21/768 ,  H01L23/532

Abstract: A semiconductor device includes a contact metallization layer arranged on a semiconductor substrate, an inorganic passivation structure arranged on the semiconductor substrate, and an organic passivation layer. The organic passivation layer is located between the contact metallization layer and the inorganic passivation structure, and located vertically closer to the semiconductor substrate than a part of the organic passivation layer located on top of the inorganic passivation structure.

公开(公告)号：US20210343835A1

公开(公告)日：2021-11-04

申请号：US17375034

申请日：2021-07-14

Applicant: Infineon Technologies AG

Inventor： Ralf Siemieniec ,  Thomas Aichinger ,  Thomas Basler ,  Wolfgang Bergner ,  Rudolf Elpelt ,  Romain Esteve ,  Michael Hell ,  Daniel Kueck ,  Caspar Leendertz ,  Dethard Peters ,  Hans-Joachim Schulze

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/16 ,  H01L21/04 ,  H01L29/66 ,  H01L29/10

Abstract: A semiconductor component includes: gate structures extending from a first surface into an SiC semiconductor body; a drift zone of a first conductivity type formed in the SiC semiconductor body; first mesas and second mesas arranged between the gate structures in the SiC semiconductor body; body areas of a second conductivity type arranged in the first mesas and the second mesas, the body areas each adjoining a first side wall of one of the gate structures; first shielding areas of the second conductivity type adjoining a second side wall of one of the gate structures; second shielding areas of the second conductivity type adjoining the body areas in the second mesas; and diode areas of the conductivity type of the drift zone, the diode areas forming Schottky contacts with a load electrode between the first shielding areas and the second shielding areas.

公开(公告)号：US10985248B2

公开(公告)日：2021-04-20

申请号：US16354973

申请日：2019-03-15

Applicant: Infineon Technologies AG

Inventor： Caspar Leendertz ,  Romain Esteve ,  Anton Mauder ,  Andreas Meiser ,  Bernd Zippelius

IPC: H01L29/16 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10

Abstract: Embodiments of SiC devices and corresponding methods of manufacture are provided. In some embodiments, the SiC device has shielding regions at the bottom of some gate trenches and non-linear junctions formed with the SiC material at the bottom of other gate trenches. In other embodiments, the SiC device has the shielding regions at the bottom of the gate trenches and arranged in rows which run in a direction transverse to a lengthwise extension of the trenches. In still other embodiments, the SiC device has the shielding regions and the non-linear junctions, and wherein the shielding regions are arranged in rows which run in a direction transverse to a lengthwise extension of the trenches.

公开(公告)号：US10361192B2

公开(公告)日：2019-07-23

申请号：US16001540

申请日：2018-06-06

Applicant: Infineon Technologies AG

Inventor： Roland Rupp ,  Romain Esteve ,  Dethard Peters

IPC: H01L27/06 ,  H01L29/739 ,  H01L29/04 ,  H01L29/10 ,  H01L29/16 ,  H01L29/40 ,  H01L29/861

Abstract: A semiconductor device with a trench gate structure in a semiconductor body with a hexagonal crystal lattice is disclosed. In an embodiment a semiconductor device includes a semiconductor body with a hexagonal crystal lattice, wherein a mean surface plane of a first surface of the semiconductor body is tilted with respect to a crystal direction of the hexagonal crystal lattice by an off-axis angle, a trench gate structure extending into the semiconductor body and at least two transistor mesas formed from portions of the semiconductor body and adjoining the trench gate structure, wherein sidewalls of the at least two transistor mesas are aligned with a (11-20) crystal plane and deviate from a normal to the mean surface plane by at most 5 degrees, and wherein each transistor mesa comprises a MOS gate channel.

公开(公告)号：US10211306B2

公开(公告)日：2019-02-19

申请号：US15866755

申请日：2018-01-10

Applicant: Infineon Technologies AG

Inventor： Ralf Siemieniec ,  Dethard Peters ,  Romain Esteve ,  Wolfgang Bergner ,  Thomas Aichinger ,  Daniel Kueck ,  Roland Rupp ,  Bernd Zippelius ,  Karlheinz Feldrapp ,  Christian Strenger

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L29/739 ,  H01L29/04 ,  H01L29/423 ,  H01L29/40 ,  H01L29/16 ,  H01L29/20

Abstract: A semiconductor device includes a semiconductor body formed from a semiconductor material with a band-gap of at least 2.0 eV, the semiconductor body having a diode region and a source region. The semiconductor device further includes a trench gate structure having a first sidewall and a second sidewall opposite the first sidewall, the first sidewall and the second sidewall extending along a common longitudinal direction. A doping concentration of a first doping type is higher in the diode region than in the source region. The trench gate structure projects from a first surface of the semiconductor body into the semiconductor body. A first portion of the second sidewall at the first surface is directly adjoined by the source region. A second portion of the second sidewall is in direct contact with the diode region. Additional semiconductor device embodiments are provided.

公开(公告)号：US20180174840A1

公开(公告)日：2018-06-21

申请号：US15846591

申请日：2017-12-19

Applicant: Infineon Technologies AG

Inventor： Ravi Keshav Joshi ,  Romain Esteve ,  Roland Rupp ,  Francisco Javier Santos Rodriguez ,  Gerald Unegg

IPC: H01L21/04 ,  H01L29/16 ,  H01L29/45 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L21/0485 ,  H01L29/0688 ,  H01L29/0692 ,  H01L29/0813 ,  H01L29/0878 ,  H01L29/1075 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/45 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/732 ,  H01L29/7395 ,  H01L29/7805 ,  H01L29/7813 ,  H01L29/8083 ,  H01L29/861 ,  H01L29/8611 ,  H01L2924/0002

Abstract: A semiconductor device includes a silicon carbide semiconductor body and a metal contact structure. Interface particles including a silicide kernel and a carbon cover on a surface of the silicide kernel are formed directly between the silicon carbide semiconductor body and the metal contact structure. Between neighboring ones of the interface particles, the metal contact structure directly adjoins the silicon carbide semiconductor body.

公开(公告)号：US09934972B2

公开(公告)日：2018-04-03

申请号：US15288349

申请日：2016-10-07

Applicant: Infineon Technologies AG

Inventor： Thomas Aichinger ,  Wolfgang Bergner ,  Romain Esteve ,  Daniel Kueck ,  Dethard Peters ,  Victorina Poenariu ,  Gerald Reinwald ,  Roland Rupp ,  Gerald Unegg

IPC: H01L21/04 ,  H01L21/02 ,  H01L21/265 ,  H01L29/78 ,  H01L29/66 ,  H01L29/16 ,  H01L29/10 ,  H01L29/40 ,  H01L29/861 ,  H01L29/06 ,  H01L21/3065 ,  H01L29/423

CPC classification number: H01L21/0475 ,  H01L21/049 ,  H01L21/3065 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/401 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66068 ,  H01L29/7813 ,  H01L29/8613

Abstract: A trench is formed that extends from a main surface into a crystalline silicon carbide semiconductor layer. A mask is formed that includes a mask opening exposing the trench and a rim section of the main surface around the trench. By irradiation with a particle beam a first portion of the semiconductor layer exposed by the mask opening and a second portion outside of the vertical projection of the mask opening and directly adjoining to the first portion are amorphized. A vertical extension of the amorphized second portion gradually decreases with increasing distance to the first portion. The amorphized first and second portions are removed.

公开(公告)号：US09917170B2

公开(公告)日：2018-03-13

申请号：US15136121

申请日：2016-04-22

Applicant: Infineon Technologies AG

Inventor： Ravi Joshi ,  Romain Esteve ,  Markus Kahn ,  Gerald Unegg

IPC: H01L21/28 ,  H01L21/44 ,  H01L29/45 ,  H01L29/16 ,  H01L21/04 ,  H01L21/265 ,  H01L21/324

CPC classification number: H01L29/45 ,  H01L21/046 ,  H01L21/0485 ,  H01L21/26506 ,  H01L21/324 ,  H01L29/1608

Abstract: A method of forming a contact structure includes providing a silicon-carbide substrate having a highly doped silicon-carbide contact region formed in the substrate and extending to a main surface of the substrate. A carbon-based contact region is formed which is in direct contact with the highly doped silicon-carbide contact region and which extends to the main surface. A conductor is formed on the carbon-based contact region such that the carbon-based contact region is interposed between the conductor and the highly doped silicon-carbide contact region. A thermal budget for forming the carbon-based contact region is maintained below a level that induces metal silicidization of the highly doped silicon-carbide contact region.

公开(公告)号：US20170345818A1

公开(公告)日：2017-11-30

申请号：US15681607

申请日：2017-08-21

Applicant: Infineon Technologies AG

Inventor： Roland Rupp ,  Romain Esteve ,  Dethard Peters

IPC: H01L27/06 ,  H01L29/739 ,  H01L29/16 ,  H01L29/10 ,  H01L29/04 ,  H01L29/40 ,  H01L29/861

CPC classification number: H01L27/0664 ,  H01L29/045 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/407 ,  H01L29/7397 ,  H01L29/8613

Abstract: A semiconductor device includes trench gate structures in a semiconductor body with hexagonal crystal lattice. A mean surface plane of a first surface is tilted to a crystal direction by an off-axis angle, wherein an absolute value of the off-axis angle is in a range from 2 degree to 12 degree. The trench gate structures extend oriented along the crystal direction. Portions of the semiconductor body between neighboring trench gate structures form transistor mesas. Sidewalls of the transistor mesas deviate from a normal to the mean surface plane by not more than 5 degree.

公开(公告)号：US20170309720A1

公开(公告)日：2017-10-26

申请号：US15136121

申请日：2016-04-22

Applicant: Infineon Technologies AG

Inventor： Ravi Joshi ,  Romain Esteve ,  Markus Kahn ,  Gerald Unegg

IPC: H01L29/45 ,  H01L21/324 ,  H01L21/265 ,  H01L29/16 ,  H01L21/04

CPC classification number: H01L29/45 ,  H01L21/046 ,  H01L21/0485 ,  H01L21/26506 ,  H01L21/324 ,  H01L29/1608

Abstract: A method of forming a contact structure includes providing a silicon-carbide substrate having a highly doped silicon-carbide contact region formed in the substrate and extending to a main surface of the substrate. A carbon-based contact region is formed which is in direct contact with the highly doped silicon-carbide contact region and which extends to the main surface. A conductor is formed on the carbon-based contact region such that the carbon-based contact region is interposed between the conductor and the highly doped silicon-carbide contact region. A thermal budget for forming the carbon-based contact region is maintained below a level that induces metal silicidization of the highly doped silicon-carbide contact region.