公开(公告)号：US10763246B2

公开(公告)日：2020-09-01

申请号：US15646189

申请日：2017-07-11

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Klaus Schiess ,  Oliver Haeberlen ,  Matteo-Alessandro Kutschak

IPC: H01L23/495 ,  H01L25/11 ,  H01L25/10 ,  H01L23/31 ,  H01L23/00 ,  H01L23/14 ,  H01L21/48 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L25/16 ,  H01L27/088 ,  H01L21/56

Abstract: A device includes a driver circuit, a first semiconductor chip monolithically integrated with the driver circuit in a first semiconductor material, and a second semiconductor chip integrated in a second semiconductor material. The second semiconductor material is a compound semiconductor.

公开(公告)号：US20130252382A1

公开(公告)日：2013-09-26

申请号：US13893937

申请日：2013-05-14

Applicant: Infineon Technologies AG

Inventor： Oliver Haeberlen ,  Klaus Schiess ,  Stefan Kramp

IPC: H01L21/50

CPC classification number: H01L23/49861 ,  H01L21/561 ,  H01L23/142 ,  H01L23/3121 ,  H01L23/315 ,  H01L23/3157 ,  H01L23/3171 ,  H01L23/3185 ,  H01L23/36 ,  H01L23/492 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49575 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/82 ,  H01L24/97 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05572 ,  H01L2224/05639 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/13099 ,  H01L2224/24226 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2224/82 ,  H01L2224/83 ,  H01L2224/19 ,  H01L2924/00 ,  H01L2224/05099

Abstract: A method of manufacturing a semiconductor device includes providing an electrically conductive carrier and placing a semiconductor chip over the carrier. The method includes applying an electrically insulating layer over the carrier and the semiconductor chip. The electrically insulating layer has a first face facing the carrier and a second face opposite to the first face. The method includes selectively removing the electrically insulating layer and applying solder material where the electrically insulating layer is removed and on the second face of the electrically insulating layer.

Abstract translation: 制造半导体器件的方法包括提供导电载体并将半导体芯片放置在载体上。 该方法包括在载体和半导体芯片上施加电绝缘层。 电绝缘层具有面向载体的第一面和与第一面相对的第二面。 该方法包括选择性地去除电绝缘层并施加去除电绝缘层并且在电绝缘层的第二面上的焊料材料。

公开(公告)号：US09484410B2

公开(公告)日：2016-11-01

申请号：US14642638

申请日：2015-03-09

Applicant: Infineon Technologies AG

Inventor： Oliver Haeberlen ,  Franz Hirler ,  Maximilian Roesch

IPC: H01L29/10 ,  H01L29/417 ,  H01L29/78 ,  H01L29/861 ,  H01L29/06 ,  H01L29/40

CPC classification number: H01L29/1045 ,  H01L29/0626 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/41775 ,  H01L29/7816 ,  H01L29/7824 ,  H01L29/7833 ,  H01L29/7835 ,  H01L29/8611

Abstract: A semiconductor component may include a semiconductor layer which has a front side and a back side, a first terminal electrode on the front side, a second terminal electrode on the back side, a first dopant region of a first conduction type on the front side, which is electrically connected to one of the terminal electrodes, a second dopant region of a second conduction type in the semiconductor layer, which is electrically connected to the other terminal electrode, a pn junction being formed between the first and second dopant regions, a dielectric layer on the back side between the semiconductor layer and the second terminal electrode, and the dielectric layer having an opening through which an electrical connection between the second terminal electrode and the first or second dopant region is passed.

Abstract translation: 半导体部件可以包括具有前侧和后侧的半导体层，前侧的第一端子电极，背面侧的第二端子电极，前侧的第一导电型的第一掺杂剂区域， 其电连接到一个端子电极，在半导体层中的第二导电类型的第二掺杂区域，其电连接到另一个端子电极，在第一和第二掺杂剂区域之间形成pn结，电介质 在所述半导体层和所述第二端子电极之间的背侧上形成层，并且所述电介质层具有通过所述第二端子电极和所述第一或第二掺杂剂区域之间的电连接的开口。

公开(公告)号：US11069782B2

公开(公告)日：2021-07-20

申请号：US16601921

申请日：2019-10-15

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Oliver Haeberlen

IPC: H01L29/40 ,  H01L21/3115 ,  H01L29/417 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10

Abstract: A semiconductor device includes a transistor in a semiconductor body having a main surface. The transistor includes a source region; a drain region; a body region; a drift zone; a gate electrode at the body region, the body region and the drift zone being disposed along a first direction between the source region and the drain region, and the first direction being parallel to the main surface; a field plate disposed in each of a plurality of field plate trenches, each of the field plate trenches having a longitudinal axis extending along the first direction; and a field dielectric layer between the field plate and the drift zone, a thickness of the field dielectric layer at a bottom of each of the field plate trenches gradually increases along the first direction, the thickness being measured along a depth direction of the plurality of field plate trenches.

公开(公告)号：US20180097074A1

公开(公告)日：2018-04-05

申请号：US15833576

申请日：2017-12-06

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Oliver Haeberlen

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/3115 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10

Abstract: A method of manufacturing a semiconductor device is providing, which includes forming a trench in a semiconductor substrate, forming an oxide layer over sidewalls and over a bottom side of the trench, performing an ion implantation process, forming a cover layer, and patterning the covering layer, thereby forming an uncovered area and a covered area of the oxide layer, respectively. The method further includes performing an isotropic etching process thereby removing portions of the uncovered area of the oxide layer and removing a part of a surface portion of the covered area adjacent to the uncovered portions, and removing remaining portions of the covering layer.

公开(公告)号：US09893158B2

公开(公告)日：2018-02-13

申请号：US15216889

申请日：2016-07-22

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Oliver Haeberlen

IPC: H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H01L21/3115 ,  H01L29/417 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08

CPC classification number: H01L29/408 ,  H01L21/31155 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/401 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66696 ,  H01L29/66704 ,  H01L29/7825

Abstract: A semiconductor device is provided that includes a transistor in a semiconductor body having a main surface. The transistor includes a source region, a drain region, a body region, a drift zone, and a gate electrode at the body region. The body region and the drift zone are disposed along a first direction between the source region and the drain region. The first direction is parallel to the main surface. The semiconductor device further includes a field plate disposed in field plate trenches extending along the first direction in the drift zone, and a field dielectric layer between the field plate and the drift zone. A thickness of the field dielectric layer gradually increases along the first direction from a portion adjacent to the source region to a portion adjacent to the drain region.

公开(公告)号：US20150041946A1

公开(公告)日：2015-02-12

申请号：US13961155

申请日：2013-08-07

Applicant: Infineon Technologies AG

Inventor： Stephan Voss ,  Alexander Breymesser ,  Hans-Joachim Schulze ,  Erich Griebl ,  Oliver Haeberlen ,  Andreas Moser

IPC: H01L29/06 ,  H01L21/761

CPC classification number: H01L29/063 ,  H01L21/761 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/66348 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813

Abstract: A semiconductor device includes a semiconductor body and an edge termination structure. The edge termination structure comprises a first oxide layer, a second oxide layer, a semiconductor mesa region between the first oxide layer and the second oxide layer, and a doped field region comprising a first section in the semiconductor mesa region, and a second section in a region below the semiconductor mesa region. The second section overlaps the first and the second oxide layers in the region below the semiconductor mesa region.

Abstract translation: 半导体器件包括半导体本体和边缘端接结构。 边缘终端结构包括第一氧化物层，第二氧化物层，第一氧化物层和第二氧化物层之间的半导体台面区域，以及包括半导体台面区域中的第一部分的掺杂场区域，以及第二部分 半导体台面区域以下的区域。 第二部分与半导体台面区域下方的区域中的第一和第二氧化物层重叠。

公开(公告)号：US10483360B2

公开(公告)日：2019-11-19

申请号：US15833576

申请日：2017-12-06

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Oliver Haeberlen

IPC: H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H01L21/3115 ,  H01L29/417 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08

Abstract: A method of manufacturing a semiconductor device is providing, which includes forming a trench in a semiconductor substrate, forming an oxide layer over sidewalls and over a bottom side of the trench, performing an ion implantation process, forming a cover layer, and patterning the covering layer, thereby forming an uncovered area and a covered area of the oxide layer, respectively. The method further includes performing an isotropic etching process thereby removing portions of the uncovered area of the oxide layer and removing a part of a surface portion of the covered area adjacent to the uncovered portions, and removing remaining portions of the covering layer.

公开(公告)号：US20170317001A1

公开(公告)日：2017-11-02

申请号：US15646189

申请日：2017-07-11

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Klaus Schiess ,  Oliver Haeberlen ,  Matteo-Alessandro Kutschak

IPC: H01L23/31 ,  H01L23/14 ,  H01L23/495 ,  H01L25/10 ,  H01L23/00 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56

Abstract: A device includes a driver circuit, a first semiconductor chip monolithically integrated with the driver circuit in a first semiconductor material, and a second semiconductor chip integrated in a second semiconductor material. The second semiconductor material is a compound semiconductor.

公开(公告)号：US09735078B2

公开(公告)日：2017-08-15

申请号：US14254139

申请日：2014-04-16

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Klaus Schiess ,  Oliver Haeberlen ,  Matteo-Alessandro Kutschak

IPC: H01L23/495 ,  H01L23/48 ,  H01L23/52 ,  H01L23/31 ,  H01L25/10 ,  H01L23/00 ,  H01L23/14 ,  H01L21/48 ,  H01L23/538 ,  H01L21/56

CPC classification number: H01L23/3157 ,  H01L21/4842 ,  H01L21/568 ,  H01L23/142 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/49513 ,  H01L23/49537 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/48 ,  H01L24/83 ,  H01L25/105 ,  H01L2224/06181 ,  H01L2224/24175 ,  H01L2224/24246 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/40137 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48137 ,  H01L2224/73263 ,  H01L2224/73267 ,  H01L2224/8382 ,  H01L2224/92244 ,  H01L2225/1029 ,  H01L2225/1047 ,  H01L2924/00 ,  H01L2924/10253 ,  H01L2924/1033 ,  H01L2924/13055 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/014

Abstract: A device includes a first semiconductor chip that is arranged over a first carrier and includes a first electrical contact. The device further includes a second semiconductor chip arranged over a second carrier and including a second electrical contact arranged over a surface of the second semiconductor chip facing the second carrier. The second carrier is electrically coupled to the first electrical contact and the second electrical contact.