公开(公告)号：US09099459B2

公开(公告)日：2015-08-04

申请号：US14015027

申请日：2013-08-30

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Takao Sato ,  Masatoshi Fukuda

IPC: H01L21/44 ,  H01L21/48 ,  H01L25/00 ,  H01L25/07

CPC classification number: H01L25/50 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/544 ,  H01L24/02 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/18 ,  H01L2223/54453 ,  H01L2223/54486 ,  H01L2224/023 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05569 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/13 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/3012 ,  H01L2224/32225 ,  H01L2224/81065 ,  H01L2224/81132 ,  H01L2224/81815 ,  H01L2224/81907 ,  H01L2224/83132 ,  H01L2224/83862 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/00 ,  H01L2924/00012

Abstract: According to one embodiment a method is provided including positioning and bonding a plurality of first semiconductor chips in a coplanar relation on a first substrate, laminating at least a plurality of second semiconductor chips on the first semiconductor chips, cutting the first substrate for separation into a discrete chip lamination, aligning an electrode pad provided on a surface of the discrete lamination with an electrode pad on a second substrate, and temporarily connecting the electrode pads on the lamination and the second substrate in an opposing relation to the first substrate, providing electrical connection between the electrode pads by a reflow process, flowing a liquid resin from the side of the first substrate towards the second substrate to seal the chip lamination and spaces between the chip lamination and the first and second substrate, and cutting the chip lamination to form a discrete device.

Abstract translation: 根据一个实施例，提供了一种方法，包括在第一基板上定位并结合共面关系中的多个第一半导体芯片，在第一半导体芯片上层叠至少多个第二半导体芯片，将第一基板切割成 离散芯片层叠，将设置在分立层叠体的表面上的电极焊盘与第二衬底上的电极焊盘对准，并且以与第一衬底相对的关系临时连接层压体和第二衬底上的电极焊盘，从而提供电连接 通过回流工艺在电极焊盘之间，将液态树脂从第一衬底的侧面朝向第二衬底流动，以密封芯片层叠和芯片层压体与第一和第二衬底之间的间隔，并且切割芯片层叠以形成 离散设备。

公开(公告)号：US09052187B2

公开(公告)日：2015-06-09

申请号：US13784334

申请日：2013-03-04

Applicant: Kabushiki Kaisha Toshiba

Inventor： Naoyuki Komuta ,  Masatoshi Fukuda

IPC: G01B11/00 ,  G01B11/14 ,  G01B11/26 ,  G01C1/00 ,  G01B11/27 ,  H01L23/00

CPC classification number: G01B11/14 ,  G01B11/272 ,  H01L24/75 ,  H01L24/81 ,  H01L2223/54426 ,  H01L2224/0401 ,  H01L2224/06155 ,  H01L2224/16145 ,  H01L2224/75753 ,  H01L2224/8113 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06593

Abstract: An apparatus relating to the manufacture of stacked semiconductor devices includes, for example, a first holding section configured to hold a first semiconductor device and a second holding section configured to hold a second semiconductor device. Additionally, a measuring section including an imaging device for acquiring images of the first and second semiconductor devices and a control section configured to control the holding sections to correct misalignment between the semiconductor devices. The control section is further configured to determine misalignment using the images of the first and second semiconductor devices when the images include a first alignment mark disposed proximate to an edge of the first semiconductor device and a second alignment mark disposed proximate to an edge of the second semiconductor device.

Abstract translation: 与叠层半导体器件的制造相关的装置例如包括构造成保持第一半导体器件的第一保持部和配置为保持第二半导体器件的第二保持部。 另外，测量部分包括用于获取第一和第二半导体器件的图像的成像装置和被配置为控制保持部分以校正半导体器件之间的未对准的控制部分。 控制部分还被配置为当图像包括靠近第一半导体器件的边缘设置的第一对准标记和靠近第二半导体器件的边缘设置的第二对准标记时，使用第一和第二半导体器件的图像来确定未对准 半导体器件。

公开(公告)号：US09721905B2

公开(公告)日：2017-08-01

申请号：US15169246

申请日：2016-05-31

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Keiju Yamada ,  Takashi Yamazaki ,  Masatoshi Fukuda ,  Yasuhiro Koshio

IPC: H01L21/00 ,  H01L23/552 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L23/544

CPC classification number: H01L23/552 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49805 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/544 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

Abstract: According to an embodiment, a semiconductor package includes a semiconductor chip mounted on an interposer board, a encapsulant sealing the semiconductor chip, and a conductive shielding layer covering the encapsulant and at least part of a side surface of the interposer board. The interposer board has plural vias through an insulating substrate. A part of the plural vias has a cutting plane exposing to the side surface of the interposer board and cut in a thickness direction of the interposer board. The cutting plane of the via is electrically connected to the conductive shielding layer.

公开(公告)号：US09224713B2

公开(公告)日：2015-12-29

申请号：US14221838

申请日：2014-03-21

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Satoshi Tsukiyama ,  Masatoshi Fukuda ,  Hiroshi Watabe ,  Keita Mizoguchi ,  Naoyuki Komuta

IPC: H01L21/44 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L21/50 ,  H01L25/065 ,  H01L25/00 ,  H01L23/31

CPC classification number: H01L24/81 ,  H01L21/50 ,  H01L23/3128 ,  H01L23/49811 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/14151 ,  H01L2224/14155 ,  H01L2224/14156 ,  H01L2224/14177 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/81139 ,  H01L2224/8114 ,  H01L2224/81141 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81201 ,  H01L2224/81203 ,  H01L2224/83104 ,  H01L2224/83815 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01083 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/00

Abstract: In one embodiment, a semiconductor device includes a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first and second semiconductor chips are electrically connected via first bump connection parts. Stopper projections and bonding projections are provided at least one of the first and second semiconductor chips. The stopper projections are in contact with the other of the first and second semiconductor chips in an unbonded state. The bonding projections are bonded to the first and second semiconductor chips.

Abstract translation: 在一个实施例中，半导体器件包括堆叠在第一半导体芯片上的第一半导体芯片和第二半导体芯片。 第一和第二半导体芯片通过第一凸块连接部电连接。 止动器突起和接合突起设置在第一和第二半导体芯片中的至少一个上。 止动突起与未粘合状态的第一和第二半导体芯片中的另一个接触。 接合突起接合到第一和第二半导体芯片。

公开(公告)号：US20130250298A1

公开(公告)日：2013-09-26

申请号：US13784334

申请日：2013-03-04

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Naoyuki KOMUTA ,  Masatoshi Fukuda

IPC: G01B11/14

CPC classification number: G01B11/14 ,  G01B11/272 ,  H01L24/75 ,  H01L24/81 ,  H01L2223/54426 ,  H01L2224/0401 ,  H01L2224/06155 ,  H01L2224/16145 ,  H01L2224/75753 ,  H01L2224/8113 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06593

Abstract: An apparatus relating to the manufacture of stacked semiconductor devices includes, for example, a first holding section configured to hold a first semiconductor device and a second holding section configured to hold a second semiconductor device. Additionally, a measuring section including an imaging device for acquiring images of the first and second semiconductor devices and a control section configured to control the holding sections to correct misalignment between the semiconductor devices. The control section is further configured to determine misalignment using the images of the first and second semiconductor devices when the images include a first alignment mark disposed proximate to an edge of the first semiconductor device and a second alignment mark disposed proximate to an edge of the second semiconductor device.

Abstract translation: 与叠层半导体器件的制造相关的装置例如包括构造成保持第一半导体器件的第一保持部和配置为保持第二半导体器件的第二保持部。 另外，测量部分包括用于获取第一和第二半导体器件的图像的成像装置和被配置为控制保持部分以校正半导体器件之间的未对准的控制部分。 控制部分还被配置为当图像包括靠近第一半导体器件的边缘设置的第一对准标记和靠近第二半导体器件的边缘设置的第二对准标记时，使用第一和第二半导体器件的图像来确定未对准 半导体器件。

公开(公告)号：US09570414B2

公开(公告)日：2017-02-14

申请号：US14474686

申请日：2014-09-02

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Satoshi Tsukiyama ,  Masatoshi Fukuda ,  Yukifumi Oyama ,  Shinya Fukayama

IPC: H01L21/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/07 ,  H01L23/544 ,  H01L21/56

CPC classification number: H01L24/81 ,  H01L21/563 ,  H01L23/544 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L25/074 ,  H01L25/50 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2224/10135 ,  H01L2224/1131 ,  H01L2224/11334 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/1319 ,  H01L2224/1403 ,  H01L2224/1415 ,  H01L2224/14505 ,  H01L2224/16146 ,  H01L2224/1705 ,  H01L2224/17517 ,  H01L2224/73204 ,  H01L2224/8113 ,  H01L2224/81139 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/81862 ,  H01L2224/81907 ,  H01L2224/83104 ,  H01L2224/92125 ,  H01L2924/35 ,  H01L2924/01083 ,  H01L2924/01049 ,  H01L2924/00014 ,  H01L2224/8185 ,  H01L2924/0665 ,  H01L2924/01047 ,  H01L2924/01029

Abstract: According to one embodiment, a first electrode is formed on a first face of a first semiconductor chip, and a second electrode and a protrusion are formed on a second face of a second semiconductor chip. The first semiconductor chip and the second semiconductor chip are spaced from one another by the protrusion in such a manner that the first face and the second face face each other. The first semiconductor chip and the second semiconductor chip are subject to reflow to be electrically connected to each other, and then the protrusion is cured at a temperature lower than a reflow temperature.

Abstract translation: 根据一个实施例，第一电极形成在第一半导体芯片的第一面上，第二电极和突起形成在第二半导体芯片的第二面上。 第一半导体芯片和第二半导体芯片通过突起彼此间隔开，使得第一面和第二面彼此面对。 第一半导体芯片和第二半导体芯片经受回流以彼此电连接，然后突起在低于回流温度的温度下固化。