Structures and methods for source-down vertical semiconductor device

    公开(公告)号:US12094967B2

    公开(公告)日:2024-09-17

    申请号:US17805131

    申请日:2022-06-02

    Inventor: Gordon M. Grivna

    Abstract: A semiconductor device includes a region of semiconductor material having a first side and a second side opposite to the first side. Active device structures are adjacent to the first side, the active device structures comprising source regions and gate electrodes. A first gate conductor is at the first side electrically connected to the gate electrodes, a drain region is at the second side, a second gate conductor is at the second side, and through-semiconductor vias extending from the first side towards the side and electrically connecting the first gate electrode to the second gate electrode. A source electrode is at the first side electrically connected to the source regions, and a drain electrode is at the second side electrically connected to the drain region. The through-semiconductor vias are electrically isolated from the source regions and the drain region. The structure provides a gate/drain up with a source-down configuration.

    Structures and methods for source-down vertical semiconductor device

    公开(公告)号:US11380788B2

    公开(公告)日:2022-07-05

    申请号:US16948880

    申请日:2020-10-05

    Inventor: Gordon M. Grivna

    Abstract: A semiconductor device includes a region of semiconductor material having a first side and a second side opposite to the first side. Active device structures are adjacent to the first side, the active device structures comprising source regions and gate electrodes. A first gate conductor is at the first side electrically connected to the gate electrodes, a drain region is at the second side, a second gate conductor is at the second side, and through-semiconductor vias extending from the first side towards the side and electrically connecting the first gate electrode to the second gate electrode. A source electrode is at the first side electrically connected to the source regions, and a drain electrode is at the second side electrically connected to the drain region. The through-semiconductor vias are electrically isolated from the source regions and the drain region. The structure provides a gate/drain up with a source-down configuration.

    Process of forming an electronic device including a polymer support layer

    公开(公告)号:US11367657B2

    公开(公告)日:2022-06-21

    申请号:US16661776

    申请日:2019-10-23

    Inventor: Gordon M. Grivna

    Abstract: A process can be used to allow processing of thin layers of a workpiece including dies. The workpiece can include a base substrate and a plurality of layers overlying the base substrate. The process can include forming a polymer support layer over the plurality of layers; thinning or removing the base substrate within a component region of the workpiece, wherein the component region includes an electronic device; and singulating the workpiece into a plurality of dies after thinning or removing the base substrate. In another aspect, an electronic device can be formed using such process. In an embodiment, the workpiece may have a size corresponding to a semiconductor wafer to allow wafer-level, as opposed to die-level, processing.

    Method of separating electronic devices having a back layer and apparatus

    公开(公告)号:US10950503B2

    公开(公告)日:2021-03-16

    申请号:US16535562

    申请日:2019-08-08

    Inventor: Gordon M. Grivna

    Abstract: A method of singulating a wafer includes providing a wafer having a plurality of die formed as part of the wafer and separated from each other by spaces, wherein the wafer has first and second opposing major surfaces, and wherein a layer of material is formed along the second major surface. The method includes placing the wafer onto a carrier substrate. The method includes singulating the wafer through the spaces to form singulation lines after the placing the wafer on the carrier substrate, wherein singulating comprises stopping in proximity to the layer of material. The method includes applying a pressure to the entire wafer thereby separating the layer of material in the singulation lines, wherein applying the pressure comprises using a fluid. The method provide a way to batch separate layers of material disposed on wafers after singulating the wafers.

    Electronic device including a temperature sensor

    公开(公告)号:US10545055B2

    公开(公告)日:2020-01-28

    申请号:US15621093

    申请日:2017-06-13

    Abstract: An electronic device can include a temperature sensor. The temperature sensor can include a drain electrode including drain fingers spaced apart from the source fingers; a source electrode including source fingers spaced apart from the drain fingers; and a gate electrode including a runner, gate fingers and a conductive bridge. In an embodiment, the runner includes a first portion and a second portion spaced apart from the first portion, the gate fingers are coupled to the runner and each gate finger is disposed between a pair of the source and drain fingers. The conductive bridge connects at least two gate fingers, wherein the conductive bridge is along a conduction path between the first and second portions of the runner. Designs for the temperature sensor may provide a more accurate temperature measurement reflective of a transistor within the electronic device.

    Method of separating electronic devices having a back layer and apparatus

    公开(公告)号:US10366923B2

    公开(公告)日:2019-07-30

    申请号:US15478839

    申请日:2017-04-04

    Inventor: Gordon M. Grivna

    Abstract: A method of singulating a wafer includes providing a wafer having a plurality of die formed as part of the wafer and separated from each other by spaces. The wafer has first and second opposing major surfaces and a layer of material disposed along the second major surface. The method includes placing the wafer onto a carrier substrate and etching through the spaces to form singulation lines, wherein etching comprises stopping atop the layer of material. The method includes providing an apparatus comprising a compression structure, a support structure, and a transducer system configured to apply high frequency mechanical vibrations to the layer of material. The method includes placing the wafer and the carrier substrate onto the support structure, and, in one embodiment, applying pressure and mechanical vibrations to the wafer to separate the layer of material in the singulation lines.

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