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1.发明公开公开(公告)号：US20240260254A1
公开(公告)日：2024-08-01
申请号：US18403103
申请日：2024-01-03
发明人： Kamal M. Karda , Haitao Liu , Si-Woo Lee , Chandra Mouli
IPC分类号： H10B12/00 , H01L23/528 , H01L29/423
CPC分类号： H10B12/33 , H01L23/5283 , H01L29/42392 , H10B12/03 , H10B12/482 , H10B12/488
摘要： Methods, apparatuses, and systems related to a memory device having transistor body contacts that extend vertically across stacked circuit layers and connect to body portions of data access transistors are described. A memory device may include storage cells and corresponding access circuits on each of the stacked layers. The vertically extending transistor body contacts may provide a route for leakage away from data storage circuits when the data access transistors are off.
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公开(公告)号：US20220069124A1
公开(公告)日：2022-03-03
申请号：US17524653
申请日：2021-11-11
发明人： Kamal M. Karda , Chandra Mouli , Haitao Liu
IPC分类号： H01L29/78 , H01L29/06 , H01L29/04 , H01L27/108 , H01L29/45 , H01L29/08 , H01L29/10 , H01L29/267
摘要： Some embodiments include an integrated assembly having a semiconductor material with a more-doped region adjacent to a less-doped region. A two-dimensional material is between the more-doped region and a portion of the less-doped region. Some embodiments include an integrated assembly which contains a semiconductor material, a metal-containing material over the semiconductor material, and a two-dimensional material between a portion of the semiconductor material and the metal-containing material. Some embodiments include a transistor having a first source/drain region, a second source/drain region, a channel region between the first and second source/drain regions, and a two-dimensional material between the channel region and the first source/drain region.
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公开(公告)号：US11121223B2
公开(公告)日：2021-09-14
申请号：US16685205
申请日：2019-11-15
发明人： Haitao Liu , Chandra Mouli
IPC分类号： H01L21/28 , H01L21/763 , G11C16/04
摘要： Field-effect transistors, and apparatus including such field-effect transistors, including a gate dielectric overlying a semiconductor and a control gate overlying the gate dielectric. The control gate might include an instance of a first polycrystalline silicon-containing material containing polycrystalline silicon, and an instance of a second polycrystalline silicon-containing material containing polycrystalline silicon-germanium or polycrystalline silicon-germanium-carbon.
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4.发明申请公开(公告)号：US20210242272A1
公开(公告)日：2021-08-05
申请号：US17154703
申请日：2021-01-21
发明人： Chandra Mouli
IPC分类号： H01L27/146 , H01L31/0352
摘要： An imager having a pixel cell having an associated strained silicon layer. The strained silicon layer increases charge transfer efficiency, decreases image lag, and improves blue response in imaging devices.
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公开(公告)号：US20210151573A1
公开(公告)日：2021-05-20
申请号：US16685205
申请日：2019-11-15
发明人： Haitao Liu , Chandra Mouli
IPC分类号： H01L21/28 , H01L21/763 , G11C16/04
摘要： Field-effect transistors, and apparatus including such field-effect transistors, including a gate dielectric overlying a semiconductor and a control gate overlying the gate dielectric. The control gate might include an instance of a first polycrystalline silicon-containing material containing polycrystalline silicon, and an instance of a second polycrystalline silicon-containing material containing polycrystalline silicon-germanium or polycrystalline silicon-germanium-carbon.
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6.发明授权公开(公告)号：US10910431B2
公开(公告)日：2021-02-02
申请号：US16161653
申请日：2018-10-16
发明人： Chandra Mouli
IPC分类号： H01L31/18 , H01L27/146 , H01L31/0352 , H01L31/11
摘要： An imager having a pixel cell having an associated strained silicon layer. The strained silicon layer increases charge transfer efficiency, decreases image lag, and improves blue response in imaging devices.
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公开(公告)号：US10607988B2
公开(公告)日：2020-03-31
申请号：US16398501
申请日：2019-04-30
IPC分类号： H01L27/112 , H01L27/07 , H01L27/108 , H01L49/02 , G11C11/4074 , H01L29/08 , H01L27/11556 , H01L21/8234 , H01L21/84 , H01L21/8238 , H01L27/11582 , G11C11/408 , H01L27/11553 , H01L29/92 , G11C5/14 , G11C5/06
摘要： Some embodiments include a memory cell with two transistors and one capacitor. The transistors are a first transistor and a second transistor. The capacitor has a first node coupled with a source/drain region of the first transistor, and has a second node coupled with a source/drain region of the second transistor. The memory cell has a first body region adjacent the source/drain region of the first transistor, and has a second body region adjacent the source/drain region of the second transistor. A first body connection line couples the first body region of the memory cell to a first reference voltage. A second body connection line couples the second body region of the memory cell to a second reference voltage. The first and second reference voltages may be the same as one another, or may be different from one another.
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公开(公告)号：US10535711B2
公开(公告)日：2020-01-14
申请号：US15792585
申请日：2017-10-24
发明人： Chandra Mouli
IPC分类号： G11C11/00 , H01L27/24 , G11C11/56 , G11C13/00 , H01L45/00 , G11C5/02 , G11C11/34 , H01L29/66
摘要： Some embodiments include memory devices having a wordline, a bitline, a memory element selectively configurable in one of three or more different resistive states, and a diode configured to allow a current to flow from the wordline through the memory element to the bitline responsive to a voltage being applied across the wordline and the bitline and to decrease the current if the voltage is increased or decreased. Some embodiments include memory devices having a wordline, a bitline, memory element selectively configurable in one of two or more different resistive states, a first diode configured to inhibit a first current from flowing from the bitline to the wordline responsive to a first voltage, and a second diode comprising a dielectric material and configured to allow a second current to flow from the wordline to the bitline responsive to a second voltage.
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公开(公告)号：US20190259769A1
公开(公告)日：2019-08-22
申请号：US16398501
申请日：2019-04-30
IPC分类号： H01L27/112 , H01L27/108 , G11C11/408 , G11C11/4074 , H01L49/02 , H01L29/08 , H01L27/11582 , H01L21/8238 , H01L21/8234 , H01L21/84 , H01L27/11556
摘要： Some embodiments include a memory cell with two transistors and one capacitor. The transistors are a first transistor and a second transistor. The capacitor has a first node coupled with a source/drain region of the first transistor, and has a second node coupled with a source/drain region of the second transistor. The memory cell has a first body region adjacent the source/drain region of the first transistor, and has a second body region adjacent the source/drain region of the second transistor. A first body connection line couples the first body region of the memory cell to a first reference voltage. A second body connection line couples the second body region of the memory cell to a second reference voltage. The first and second reference voltages may be the same as one another, or may be different from one another.
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公开(公告)号：US20190181143A1
公开(公告)日：2019-06-13
申请号：US16279262
申请日：2019-02-19
发明人： Deepak Chandra Pandey , Haitao Liu , Chandra Mouli , Sanh D. Tang
IPC分类号： H01L27/108 , H01L29/78
摘要： Some embodiments include an apparatus having a transistor associated with a vertically-extending semiconductor pillar. The transistor includes an upper source/drain region within the vertically-extending semiconductor pillar, a lower source/drain region within the vertically-extending semiconductor pillar, and a channel region within the vertically-extending semiconductor pillar and between the upper and lower source/drain regions. The transistor also includes a gate along the channel region. A wordline is coupled with the gate of the transistor. A digit line is coupled with the lower source/drain region of the transistor. A programmable device is coupled with the upper source/drain region of the transistor. A body connection line is over the wordline and extends parallel to the wordline. The body connection line has a lateral edge that penetrates into the vertically-extending semiconductor material pillar. The body connection line is of a different composition than the semiconductor material pillar.
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