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    Wear leveling for random access and ferroelectric memory
    2.
    发明授权
    Wear leveling for random access and ferroelectric memory 有权

    公开(公告)号：US10971203B2

    公开(公告)日：2021-04-06

    申请号：US16504837

    申请日：2019-07-08

    Applicant: Micron Technology, Inc.

    Inventor： Richard E. Fackenthal ,  Daniele Vimercati ,  Duane R. Mills

    IPC: G11C29/00 ,  G11C11/22 ,  G06F11/10 ,  G11C29/52

    Abstract: Methods, systems, and devices related to wear leveling for random access and ferroelectric memory are described. Non-volatile memory devices, e.g., ferroelectric random access memory (FeRAM) may utilize wear leveling to extend life time of the memory devices by avoiding reliability issues due to a limited cycling capability. A wear-leveling pool, or number of cells used for a wear-leveling application, may be expanded by softening or avoiding restrictions on a source page and a destination page within a same section of memory array. In addition, error correction code may be applied when moving data from the source page to the destination page to avoid duplicating errors present in the source page.

    Techniques for sensing logic values stored in memory cells using sense amplifiers that are selectively isolated from digit lines
    4.
    发明授权
    Techniques for sensing logic values stored in memory cells using sense amplifiers that are selectively isolated from digit lines 有权

    公开(公告)号：US10410709B2

    公开(公告)日：2019-09-10

    申请号：US15855152

    申请日：2017-12-27

    Applicant: Micron Technology, Inc.

    Inventor： Daniele Vimercati ,  Duane R. Mills

    IPC: G11C11/22 ,  G11C7/10

    Abstract: Methods, systems, and devices for operating an electronic memory apparatus are described. A logic value stored in a ferroelectric random access memory (FeRAM) cell is read onto a first sensing node of a sense amplifier. The reading is performed through a digit line coupling the FeRAM cell to the first sensing node, while the sense amplifier is in an inactive state. A second sensing node of the sense amplifier is biased to a reference voltage provided by a reference voltage source. The biasing is performed while reading the logic value stored in the FeRAM cell onto the first sensing node. The digit line is isolated from the first sensing node after the reading. The sense amplifier is activated, after isolating the digit line from the first sensing node, to amplify and sense a voltage difference between the first sensing node and the second sensing node.

    MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND SHIELD STRUCTURES
    6.
    发明申请
    MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND SHIELD STRUCTURES 有权

    公开(公告)号：US20240420750A1

    公开(公告)日：2024-12-19

    申请号：US18818295

    申请日：2024-08-28

    Applicant: Micron Technology, Inc.

    Inventor： Kamal M. Karda ,  Haitao Liu ,  Karthik Sarpatwari ,  Durai Vishak Nirmal Ramaswamy ,  Alessandro Calderoni ,  Richard E. Fackenthal ,  Duane R. Mills

    IPC: G11C11/404

    Abstract: Some embodiments include apparatuses in which one of such apparatus includes a first memory cell including a first transistor having a first channel region coupled between a data line and a conductive region, and a first charge storage structure located between the first data line and the conductive region, and a second transistor having a second channel region coupled to and located between the first data line and the first charge storage structure; a second memory cell including a third transistor having a third channel region coupled between a second data line and the conductive region, and a second charge storage structure located between the second data line and the conductive region, and a fourth transistor having a fourth channel region coupled to and located between the second data line and the second charge storage structure; a conductive line forming a gate of each of the first, second, third, and fourth transistors; and a conductive structure located between the first and second charge storage structures and electrically separated from the conductive region.

    Wear leveling for random access and ferroelectric memory
    8.
    发明授权
    Wear leveling for random access and ferroelectric memory 有权

    公开(公告)号：US11605412B2

    公开(公告)日：2023-03-14

    申请号：US17196650

    申请日：2021-03-09

    Applicant: Micron Technology, Inc.

    Inventor： Richard E. Fackenthal ,  Daniele Vimercati ,  Duane R. Mills

    IPC: G11C11/22 ,  G06F11/10 ,  G11C29/52

    Abstract: Methods, systems, and devices related to wear leveling for random access and ferroelectric memory are described. Non-volatile memory devices, e.g., ferroelectric random access memory (FeRAM) may utilize wear leveling to extend life time of the memory devices by avoiding reliability issues due to a limited cycling capability. A wear-leveling pool, or number of cells used for a wear-leveling application, may be expanded by softening or avoiding restrictions on a source page and a destination page within a same section of memory array. In addition, error correction code may be applied when moving data from the source page to the destination page to avoid duplicating errors present in the source page.

    Memory cell sensing stress mitigation
    9.
    发明授权
    Memory cell sensing stress mitigation 有权

    公开(公告)号：US11222668B1

    公开(公告)日：2022-01-11

    申请号：US17004402

    申请日：2020-08-27

    Applicant: Micron Technology, Inc.

    Inventor： Daniele Vimercati ,  Duane R. Mills ,  Richard E. Fackenthal ,  Yasuko Hattori

    IPC: G11C11/22 ,  G11C11/56 ,  G11C7/06 ,  G11C7/10 ,  G11C7/14

    Abstract: Methods, systems, and devices for memory cell sensing stress mitigation are described. A memory device may be configured to bias a memory cell to a voltage with a first polarity or a second polarity (e.g., a positive voltage or a negative voltage) during an access operation to level wear experienced by the memory cell during the access operation. For example, during a first read operation, a first pulse with the first polarity (e.g., a negative voltage) may be applied to the memory cell to read out a first logic state stored at the memory cell. During a second read operation, a second pulse with the second polarity (e.g., a positive voltage) may be applied to the memory cell to read out a second logic state stored at the memory cell. The memory device may include a selection component for selecting between the different pulses used for different read operations.

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