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公开(公告)号：US11765912B2
公开(公告)日：2023-09-19
申请号：US17187213
申请日：2021-02-26
CPC分类号： H10B63/20 , H10B63/30 , H10B63/845 , H10B69/00 , H10N70/20 , H10N70/231 , H10N70/8828 , H10N70/8836
摘要： In an example, a memory array may include a plurality of first dielectric materials and a plurality of stacks, where each respective first dielectric material and each respective stack alternate, and where each respective stack comprises a first conductive material and a storage material. A second conductive material may pass through the plurality of first dielectric materials and the plurality of stacks. Each respective stack may further include a second dielectric material between the first conductive material and the second conductive material.
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公开(公告)号：US20220036946A1
公开(公告)日：2022-02-03
申请号：US17399853
申请日：2021-08-11
摘要： Methods, systems, and devices related to a multi-level self-selecting memory device are described. A self-selecting memory cell may store one or more bits of data represented by different threshold voltages of the self-selecting memory cell. A programming pulse may be varied to establish the different threshold voltages by modifying one or more durations during which a fixed level of voltage or fixed level of current is maintained across the self-selecting memory cell. The self-selecting memory cell may include a chalcogenide alloy. A non-uniform distribution of an element in the chalcogenide alloy may determine a particular threshold voltage of the self-selecting memory cell. The shape of the programming pulse may be configured to modify a distribution of the element in the chalcogenide alloy based on a desired logic state of the self-selecting memory cell.
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公开(公告)号：US10950284B2
公开(公告)日：2021-03-16
申请号：US16731948
申请日：2019-12-31
发明人： Andrea Redaelli , Fabio Pellizzer
摘要： Methods, systems, and devices for a decoder are described. The memory device may include a substrate, an array of memory cells coupled with the substrate, and a decoder coupled with the substrate. The decoder may be configured to apply a voltage to an access line of the array of memory cells as part of an access operation. The decoder may include a first conductive line configured to carry the voltage applied to the access line of the array of memory cells. In some cases, the decoder may include a doped material extending between the first conductive line and the access line of the array of memory cells in a first direction (e.g., away from a surface of the substrate) and the doped material may be configured to selectively couple the first conductive line of the decoder with the access line of the array of memory cells.
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公开(公告)号：US10896932B2
公开(公告)日：2021-01-19
申请号：US16513797
申请日：2019-07-17
摘要： The present disclosure includes three dimensional memory arrays, and methods of processing the same. A number of embodiments include a plurality of conductive lines separated from one other by an insulation material, a plurality of conductive extensions arranged to extend substantially perpendicular to the plurality of conductive lines, and a storage element material formed around each respective one of the plurality of conductive extensions and having two different contacts with each respective one of the plurality of conductive lines, wherein the two different contacts with each respective one of the plurality of conductive lines are at two different ends of that respective conductive line.
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公开(公告)号：US20200303640A1
公开(公告)日：2020-09-24
申请号：US16877154
申请日：2020-05-18
摘要： Methods, systems, and devices for a tapered cell profile and fabrication are described. A memory storage component may contain multiple chalcogenide materials and may include a tapered profile. For example, a first chalcogenide material may be coupled with a second chalcogenide material. Each of the chalcogenide materials may be further coupled with a conductive material (e.g., an electrode). Through an etching process, the chalcogenide materials may tapered (e.g., step tapered). A pulse may be applied to the tapered chalcogenide materials resulting in a memory storage component that includes a mixture of the chalcogenide materials.
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公开(公告)号：US10693066B2
公开(公告)日：2020-06-23
申请号：US16429959
申请日：2019-06-03
摘要： Subject matter described pertains to methods, apparatuses, and circuits for programming a memory device.
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公开(公告)号：US20200176512A1
公开(公告)日：2020-06-04
申请号：US16785026
申请日：2020-02-07
摘要： An example three-dimensional (3-D) memory array includes a first plurality of conductive lines separated from one other by an insulation material, a second plurality of conductive lines, and a plurality of pairs of conductive pillars arranged to extend substantially perpendicular to the first plurality of conductive lines and the second plurality of conductive lines. The conductive pillars of each respective pair are coupled to a same conductive line of the second plurality of conductive lines. A storage element material is formed partially around the conductive pillars of each respective pair.
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公开(公告)号：US20200013472A1
公开(公告)日：2020-01-09
申请号：US16536107
申请日：2019-08-08
发明人： Andrea Redaelli
摘要： Embodiments disclosed herein relate to operating a memory cell as an anti-fuse, such as for use in phase change memory, for example.
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公开(公告)号：US10510957B2
公开(公告)日：2019-12-17
申请号：US15660829
申请日：2017-07-26
发明人： Agostino Pirovano , Fabio Pellizzer , Anna Maria Conti , Andrea Redaelli , Innocenzo Tortorelli
摘要： A multi-layer memory device with an array having multiple memory decks of self-selecting memory cells is provided in which N memory decks may be fabricated with N+1 mask operations. The multiple memory decks may be self-aligned and certain manufacturing operations may be performed for multiple memory decks at the same time. For example, patterning a bit line direction of a first memory deck and a word line direction in a second memory deck above the first memory deck may be performed in a single masking operation, and both decks may be etched in a same subsequent etching operation. Such techniques may provide efficient fabrication which may allow for enhanced throughput, additional capacity, and higher yield for fabrication facilities relative to processing techniques in which each memory deck is processed using two or more mask and etch operations per memory deck.
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公开(公告)号：US20190355904A1
公开(公告)日：2019-11-21
申请号：US16429959
申请日：2019-06-03
摘要： Subject matter described pertains to methods, apparatuses, and circuits for programming a memory device.
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