公开(公告)号：US20250046390A1

公开(公告)日：2025-02-06

申请号：US18774447

申请日：2024-07-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fulvio Rori ,  Pitamber Shukla ,  Chiara Cerafogli ,  Erasmo Jose B. Vargas

IPC: G11C29/12

Abstract: A methods and system directed to a wordline ramp rate monitor for early detection of defect activation are disclosed. A memory access directed to a wordline is initiated. Based on an applied ramping voltage, a ramp rate of the wordline is determined. Responsive to determining that the ramp rate satisfied a defect condition, the memory access operation is aborted.

公开(公告)号：US12153490B2

公开(公告)日：2024-11-26

申请号：US17566921

申请日：2021-12-31

Applicant: Micron Technology, Inc.

Inventor： Priya Venkataraman ,  Pitamber Shukla ,  Vipul Patel ,  Scott A. Stoller

IPC: G11C16/34 ,  G06F3/06 ,  G06F11/07 ,  G06F11/10 ,  G06F12/0882 ,  G11C29/04 ,  G11C29/44

Abstract: Read calibration by sector of memory can include reading a page of memory, having more than one sector, with a read level, such as a default read level. In response to an error, such as an uncorrectable error correction code read result, the respective read level can be calibrated for each sector to yield a respective calibrated read level per sector. The page of memory can be read with the respective calibrated read level per sector. The calibrated read levels can be stored.

公开(公告)号：US20240248616A1

公开(公告)日：2024-07-25

申请号：US18624657

申请日：2024-04-02

Applicant: Micron Technology, Inc.

Inventor： Sandeep Reddy Kadasani ,  Pitamber Shukla ,  Scott Anthony Stoller ,  Niccolo' Righetti

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/064 ,  G06F3/0653 ,  G06F3/0688

Abstract: A set of threshold voltage distribution width measurements are obtained for a block in a memory device. An endurance estimate is determined for the block based on the threshold voltage distribution width measurements. The endurance estimate comprises an indication of an estimated number of program/erase cycles during which data can be reliably stored by the block. One or more parameters of the block are managed based on the endurance estimate.

公开(公告)号：US20230197157A1

公开(公告)日：2023-06-22

申请号：US17741189

申请日：2022-05-10

Applicant: Micron Technology, Inc.

Inventor： Sandeep Kadasani ,  Pitamber Shukla ,  Scott A. Stoller ,  Renato Padilla ,  Chi Ming Chu

IPC: G11C16/08 ,  G11C16/34 ,  G11C16/30

CPC classification number: G11C16/08 ,  G11C16/30 ,  G11C16/3495

Abstract: A method includes determining, for a set of memory cells of a word line group, a parameter corresponding to a quality of the set of memory cells of the word line group and determining, for the set of memory cells, a range of voltage offset values corresponding to the parameter. The method can further include determining a voltage offset to be applied to the set of memory cells of the word line group based on the parameter or the range of voltage offset values, or both and applying a signal corresponding to the determined voltage offset to the set of memory cells of the word line group.

公开(公告)号：US11443812B2

公开(公告)日：2022-09-13

申请号：US17127358

申请日：2020-12-18

Applicant: Micron Technology, Inc.

Inventor： Scott A. Stoller ,  Pitamber Shukla ,  Priya Venkataraman ,  Giuseppina Puzzilli ,  Niccolo′ Righetti

IPC: G11C16/16 ,  G11C16/34 ,  G11C16/04

Abstract: A method is described that includes performing a first erase operation on a set of memory cells of a memory device using an erase voltage, which is set to a first voltage value and adjusting the erase voltage to a second voltage value based on feedback from performance of at least the first erase operation. The method further includes performing a second erase operation on the set of memory cells using the erase voltage, which is set to the second voltage value. In this configuration, the erase voltage set to the second voltage value is an initial voltage applied to the set of memory cells to perform erase operations such that each subsequent erase operation on the set of memory cells following the first erase operation uses an erase voltage that is equal to or greater than the second voltage value when erasing the first set of memory cells.

公开(公告)号：US12124705B2

公开(公告)日：2024-10-22

申请号：US17848061

申请日：2022-06-23

Applicant: Micron Technology, Inc.

Inventor： Pitamber Shukla ,  Ching-Huang Lu ,  Devin Batutis

IPC: G06F3/06 ,  G06F11/00 ,  G06F11/07

CPC classification number: G06F3/0619 ,  G06F3/0608 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/002 ,  G06F11/076

Abstract: Various embodiments provide for performing a memory operation, such as a memory block compaction operation or block folding or refresh operation, based on a temperature associated with a memory block of a memory device. For instance, some embodiments provide for techniques that can cause performance of a block compaction operation on a memory block at a temperature that is at least at or higher than a predetermined temperature value. Additionally, some embodiments provide for techniques that can cause performance of a block folding/refresh operation, at a temperature that is at or higher than the predetermined temperature value, on one or more blocks on which data was written at a temperature lower than the predetermined temperature value.

公开(公告)号：US20240347084A1

公开(公告)日：2024-10-17

申请号：US18755033

申请日：2024-06-26

Applicant: Micron Technology, Inc.

Inventor： Robert W. Mason ,  Pitamber Shukla ,  Steven Michael Kientz

IPC: G11C7/10 ,  G11C7/22

CPC classification number: G11C7/1096 ,  G11C7/1069 ,  G11C7/109 ,  G11C7/222

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including initializing the memory device; selecting at least one sample management unit on the memory device; performing a calibration operation on the sample management unit to determine a duration value reflecting a duration during which the memory device was powered down; adjusting an accumulator value based on the duration value; determining a read voltage value based on the accumulator value; and performing a read operation using the read voltage value.

公开(公告)号：US12057190B2

公开(公告)日：2024-08-06

申请号：US17897438

申请日：2022-08-29

Applicant: Micron Technology, Inc.

Inventor： Robert W. Mason ,  Pitamber Shukla ,  Steven Michael Kientz

IPC: G11C16/10 ,  G11C7/10 ,  G11C7/22

CPC classification number: G11C7/1096 ,  G11C7/1069 ,  G11C7/109 ,  G11C7/222

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including periodically, at a predefined frequency, incrementing a value stored in an accumulator by a composite parameter value; responsive to receiving a program request specifying a data item to be programmed to a management unit of the memory device, obtaining a first value from the accumulator; storing the first value to a program reference table; programming the data item to the management unit; responsive to receiving a read request specifying the management unit, obtaining a second value from the accumulator; determining a read voltage value based on a difference of the first value and the second value; and performing a read operation, using the read voltage value, on the management unit.

公开(公告)号：US20240256142A1

公开(公告)日：2024-08-01

申请号：US18420491

申请日：2024-01-23

Applicant: Micron Technology, Inc.

Inventor： Chun Sum Yeung ,  Pitamber Shukla ,  Zhongyuan Lu ,  Niccolo' Righetti

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/064 ,  G06F3/0679

Abstract: Methods, systems, and devices for managing partially programmed blocks are described. Based on writing data stored in a first block to a second block, a determination of whether to program the first block into a fully programmed state may be made based on whether the first block is storing the data in the partially programmed state. Based on determining whether to program the first block, the first block may be maintained in the fully programmed state until an erase operation is performed for the first block.

公开(公告)号：US20240194270A1

公开(公告)日：2024-06-13

申请号：US18528337

申请日：2023-12-04

Applicant: Micron Technology, Inc.

Inventor： Qun Su ,  Pitamber Shukla ,  Ryan Hrinya ,  Fulvio Rori ,  Jose Nino N. Monje

IPC: G11C16/16 ,  G11C16/04 ,  G11C16/08

CPC classification number: G11C16/16 ,  G11C16/0483 ,  G11C16/08

Abstract: A method includes determining that a first group of word lines associated with a block of memory cells are in a programmed state and determining that a second group of word lines associated with the block of memory cells are in an unprogrammed state. The method further includes applying a first debiasing voltage to the first group of word lines based on the determination that the first group of word lines are in the programmed state and applying a second debiasing voltage to the second group of word lines based on the determination that the second group of word lines are in the unprogrammed state.