公开(公告)号：US12223190B2

公开(公告)日：2025-02-11

申请号：US18370342

申请日：2023-09-19

Applicant: Micron Technology, Inc.

Inventor： Patrick R. Khayat ,  Steven Michael Kientz ,  Sivagnanam Parthasarathy ,  Mustafa N. Kaynak ,  Vamsi Pavan Rayaprolu

IPC: G06F3/06

Abstract: A processing device in a memory sub-system detects an occurrence of a triggering event, determines respective levels of charge loss associated with a first representative wordline of a block of a memory device and with a second representative wordline of the block of the memory device, and determines whether a difference between the respective levels of charge loss satisfies a threshold criterion. Responsive to determining that the difference between the respective levels of charge loss satisfies the threshold criterion, the processing device further determines that the block is in a uniform charge loss state.

公开(公告)号：US20240384168A1

公开(公告)日：2024-11-21

申请号：US18785912

申请日：2024-07-26

Applicant: Micron Technology, Inc.

Inventor： Mustafa N. Kaynak ,  Patrick R. Khayat ,  Sivagnanam Parthasarathy

IPC: C09K13/00 ,  C09K15/30 ,  G03F7/42

Abstract: Embodiments disclosed can include determining, for each wordline group of one or more wordline groups of the plurality of wordlines, a target adjustment to a parameter of a memory access operation that is performed with respect to a memory cell associated with a wordline of the wordline group; and responsive to determining that an aggregate read window budget (RWB) increase for the block satisfies a threshold range associated with a target RWB increase, modifying the parameter of the memory access operation according to the target adjustment, wherein the target RWB increase is determined using a different PV voltage offset for each respective programming level of the memory cell associated with the wordline of the wordline group.

公开(公告)号：US12119062B2

公开(公告)日：2024-10-15

申请号：US17884113

申请日：2022-08-09

Applicant: Micron Technology, Inc.

Inventor： Mustafa N. Kaynak ,  Patrick R. Khayat ,  Sivagnanam Parthasarathy

IPC: G11C16/08 ,  G06F3/06 ,  G11C16/10 ,  G11C16/34 ,  G11C16/04

CPC classification number: G11C16/08 ,  G06F3/0604 ,  G06F3/0655 ,  G06F3/0679 ,  G11C16/10 ,  G11C16/3459 ,  G11C16/0483

Abstract: Embodiments disclosed can include determining, for a wordline of the plurality of wordlines, a respective value of a sensitivity metric that reflects a sensitivity of a threshold voltage of a memory cell associated with the wordline to a change in a threshold voltage of an adjacent memory cell. Embodiments can also include determining, for the wordline, that the respective value of the sensitivity metric satisfies a threshold criterion. Embodiments can further include responsive to determining that the respective value of the sensitivity metric satisfies the threshold criterion, associating the wordline with a first wordline group, wherein the first wordline group comprises one or more wordlines, and wherein each wordline of the one or more wordlines is associated with a respective value of the sensitivity metric that satisfies the threshold criterion. Embodiments can include performing, on a specified memory cell connected to the wordline associated with the first wordline group, a compensatory operation.

公开(公告)号：US20240296092A1

公开(公告)日：2024-09-05

申请号：US18655091

申请日：2024-05-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Vamsi Pavan Rayaprolu ,  Dung Viet Nguyen ,  Zixiang Loh ,  Sampath K. Ratnam ,  Patrick R. Khayat ,  Thomas Herbert Lentz

IPC: G06F11/10

CPC classification number: G06F11/1044

Abstract: A request to access data programmed to a memory sub-system is received. A determination is made of whether a memory device that stores the data referenced by the request satisfies a weak memory device criterion in view of a quality rating for the device. In response to a determination that the memory device satisfies the weak memory device criterion, an error correction operation to access the data is performed in accordance with the request.

公开(公告)号：US20230176741A1

公开(公告)日：2023-06-08

申请号：US17979534

申请日：2022-11-02

Applicant: Micron Technology, Inc.

Inventor： Jeffrey S. McNeil ,  Eric N. Lee ,  Vamsi Pavan Rayaprolu ,  Sivagnanam Parthasarathy ,  Kishore Kumar Muchherla ,  Patrick R. Khayat ,  Violante Moschiano

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0679 ,  G06F3/0653

Abstract: Described are systems and methods for validating read level voltage in memory devices. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines; and a controller coupled to the memory array, the controller to perform operations comprising: causing a read level voltage to be applied to a specified wordline of the plurality of wordlines; receiving an actual bit count reflecting a number of memory cells that have their respective threshold voltages below the read level voltage; and responsive to determining that a difference of an expected bit count and the actual bit count exceeds a predetermined threshold value, adjusting the read level voltage.

公开(公告)号：US20230145358A1

公开(公告)日：2023-05-11

申请号：US17978890

申请日：2022-11-01

Applicant: Micron Technology, Inc.

Inventor： Jeffrey S. McNeil ,  Sivagnanam Parthasarathy ,  Kishore Kumar Muchherla ,  Patrick R. Khayat ,  Sead Zildzic ,  Violante Moschiano ,  James Fitzpatrick

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0679 ,  G06F3/064

Abstract: A method includes receiving, by control logic of a memory device, a copyback clear command from a processing device; causing, in response to the copyback clear command, a page buffer to perform a dual-strobe read operation on first memory cells configured as single-level cells, the dual-strobe read operation including a soft strobe at a first threshold voltage and a hard strobe at a second threshold voltage that are sensed between threshold voltage distributions of the first memory cells; causing the page buffer to determine a number of one bit values within the threshold voltage distributions detected in a threshold voltage range between the first/second threshold voltages; and causing, in response to the number of one bit values not satisfying a threshold criterion, a copyback of data in the first memory cells to second memory cells configured as high-level cells without intervention from the processing device.

公开(公告)号：US11334413B2

公开(公告)日：2022-05-17

申请号：US16752859

申请日：2020-01-27

Applicant: Micron Technology, Inc.

Inventor： Sivagnanam Parthasarathy ,  Mustafa N. Kaynak ,  Patrick R. Khayat ,  Nicholas J. Richardson

IPC: G06F11/07 ,  H03M13/00 ,  H03M13/37 ,  H03M13/11 ,  G11C11/56 ,  G06F11/10 ,  G11C29/52 ,  G11C29/56 ,  G06F11/08 ,  G11C29/00 ,  G11C29/04

Abstract: The present disclosure includes apparatuses and methods for estimating an error rate associated with memory. A number of embodiments include sensing data stored in a memory, performing an error detection operation on the sensed data, determining a quantity of parity violations associated with the error detection operation, and estimating an error rate associated with the memory based on the determined quantity of parity violations.

公开(公告)号：US10811090B2

公开(公告)日：2020-10-20

申请号：US15987414

申请日：2018-05-23

Applicant: Micron Technology, Inc.

Inventor： Sivagnanam Parthasarathy ,  Patrick R. Khayat ,  Mustafa N. Kaynak ,  Robert B. Eisenhuth

IPC: G11C16/26 ,  G11C11/56 ,  G11C16/06 ,  G11C16/34 ,  G06F11/10 ,  G11C16/04 ,  G11C29/52

Abstract: A memory cell can have a state in a valley between adjacent data states. A determination can be made whether a state of a memory cell is in a valley between adjacent distributions of states associated with respective data states. A signal indicative of a data state of the memory cell and whether the state of the memory cell is in the valley can be transmitted.

公开(公告)号：US20200176054A1

公开(公告)日：2020-06-04

申请号：US16782862

申请日：2020-02-05

Applicant: Micron Technology, Inc.

Inventor： Sivagnanam Parthasarathy ,  Patrick R. Khayat ,  Mustafa N. Kaynak

IPC: G11C11/56 ,  G06F12/02 ,  G11C16/04 ,  G06F3/06 ,  G06F11/10 ,  G11C29/16

Abstract: Apparatuses and methods for determining soft data for fractional digit memory cells are provided. One example apparatus can include a controller to determine states of memory cells of a group of memory cells operated as fractional digit memory cells, and determine soft data based, at least partially, on dimensions to which particular memory cells correspond with respect to the group of memory cells, determined states of the memory cells with respect to a state adjacent a state corresponding to a swapping shell, and whether a particular memory cell is a candidate for swapping.

公开(公告)号：US20200159616A1

公开(公告)日：2020-05-21

申请号：US16752859

申请日：2020-01-27

Applicant: Micron Technology, Inc.

Inventor： Sivagnanam Parthasarathy ,  Mustafa N. Kaynak ,  Patrick R. Khayat ,  Nicholas J. Richardson

IPC: G06F11/10 ,  G11C29/00 ,  G06F11/08 ,  G06F11/07 ,  G11C29/56 ,  G11C29/52 ,  H03M13/00 ,  H03M13/37 ,  G11C11/56 ,  H03M13/11

Abstract: The present disclosure includes apparatuses and methods for estimating an error rate associated with memory. A number of embodiments include sensing data stored in a memory, performing an error detection operation on the sensed data, determining a quantity of parity violations associated with the error detection operation, and estimating an error rate associated with the memory based on the determined quantity of parity violations.