公开(公告)号：US20240265979A1

公开(公告)日：2024-08-08

申请号：US18636901

申请日：2024-04-16

Applicant: Micron Technology, Inc.

Inventor： James Fitzpatrick ,  Phong Sy Nguyen ,  Dung Viet Nguyen ,  Sivagnanam Parthasarathy

IPC: G11C16/34 ,  A63B24/00 ,  G11C16/26

CPC classification number: G11C16/3404 ,  A63B24/0075 ,  G11C16/26 ,  A63B2024/0068 ,  A63B2024/0093 ,  A63B2220/836 ,  A63B2230/06

Abstract: A memory system configured to dynamically adjust the amount of redundant information stored in memory cells of a wordline on an integrated circuit die based on a bit error rate. For example, in response to a determination that a bit error rate of the wordline is above a threshold, the memory system can store first data items as independent first codewords of an error correction code technique into a first portion of the memory cells of the wordline, generate second data items as redundant information from the first codewords, and store the second data items in a second portion of the memory cells of the wordline. If the bit error rate is below the threshold, third data items can be stored as independent second codewords of the same length as the first codewords in the memory cells of the wordline.

公开(公告)号：US20240029801A1

公开(公告)日：2024-01-25

申请号：US18211802

申请日：2023-06-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Dung Viet Nguyen ,  Patrick R. Khayat ,  Zhengang Chen ,  Shantilal Rayshi Doru ,  Hope Abigail Henry

IPC: G11C16/34 ,  G11C16/26

CPC classification number: G11C16/3404 ,  G11C16/26

Abstract: Described are systems and methods for memory read calibration based on memory device-originated metrics characterizing voltage distributions. An example memory device includes: a memory array having a plurality of memory cells and a controller coupled to the memory array. The controller is to perform operations including: receiving a first metric characterizing threshold voltage distributions of a subset of the plurality of memory cells; determining a first read voltage adjustment; receiving a second metric characterizing the threshold voltage distributions; determining a second read voltage adjustment; and applying the second read voltage adjustment for reading the subset of the plurality of memory cells.

公开(公告)号：US20240296092A1

公开(公告)日：2024-09-05

申请号：US18655091

申请日：2024-05-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Vamsi Pavan Rayaprolu ,  Dung Viet Nguyen ,  Zixiang Loh ,  Sampath K. Ratnam ,  Patrick R. Khayat ,  Thomas Herbert Lentz

IPC: G06F11/10

CPC classification number: G06F11/1044

Abstract: A request to access data programmed to a memory sub-system is received. A determination is made of whether a memory device that stores the data referenced by the request satisfies a weak memory device criterion in view of a quality rating for the device. In response to a determination that the memory device satisfies the weak memory device criterion, an error correction operation to access the data is performed in accordance with the request.

公开(公告)号：US20230335201A1

公开(公告)日：2023-10-19

申请号：US18135915

申请日：2023-04-18

Applicant: Micron Technology, Inc.

Inventor： Tomoharu Tanaka ,  James Fitzpatrick ,  Huai-Yuan Tseng ,  Kishore Kumar Muchherla ,  Eric N. Lee ,  David Scott Ebsen ,  Dung Viet Nguyen ,  Akira Goda

IPC: G11C16/26 ,  G11C16/10 ,  G11C16/08

CPC classification number: G11C16/26 ,  G11C16/102 ,  G11C16/08

Abstract: A method includes causing a read operation to be initiated with respect to a set of target cells. For each target cell, a respective group of adjacent cells is adjacent to the target cell. The method further includes obtaining, for each group of adjacent cells, respective cell state information, assigning, based on the cell state information, each target cell of the set of target cells to a respective state information bin, and determining a set of calibrated read level offsets. Each state information bin is associated with a respective group of target cells of the set of target cells, and each calibrated read level offset of the set of calibrated read level offsets is associated with a respective state information bin of the set of state information bins.

公开(公告)号：US20250013529A1

公开(公告)日：2025-01-09

申请号：US18747234

申请日：2024-06-18

Applicant: Micron Technology, Inc.

Inventor： Dung Viet Nguyen ,  James Fitzpatrick ,  Huai-Yuan Tseng

IPC: G06F11/10

Abstract: A system can include a memory device and a processing device, operatively coupled with the memory device, to perform operations including storing a set of user data and multiple portions of error correction data. The operations can also include, responsive to an expiration of a first threshold amount of time after storing the set of user data, performing, using the third portion of the error correction data, a first error correction operation, on each of the set of user data, the first portion, and the second portion, and rewriting, on the memory device, the set of user data, the first portion, and the second portion. The operations can further include deleting the third portion.

公开(公告)号：US20240330105A1

公开(公告)日：2024-10-03

申请号：US18615592

申请日：2024-03-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Phong S. Nguyen ,  Dung Viet Nguyen ,  James Fitzpatrick ,  Sivagnanam Parthasarathy ,  Zhengang Chen

IPC: G06F11/10

CPC classification number: G06F11/1004 ,  G06F11/1068

Abstract: Input data is received for storage by a system. The input data is encoded using a low-density parity-check (LDPC) matrix to generate encoded data, wherein the LDPC matrix is selected from a plurality of LDPC matrices, each of the plurality of LDPC matrices having a common size and a unique degree distribution. The encoded data is then stored on a memory device of the system.

公开(公告)号：US11984171B2

公开(公告)日：2024-05-14

申请号：US17841096

申请日：2022-06-15

Applicant: Micron Technology, Inc.

Inventor： James Fitzpatrick ,  Phong Sy Nguyen ,  Dung Viet Nguyen ,  Sivagnanam Parthasarathy

IPC: G11C7/00 ,  A63B24/00 ,  G11C16/26 ,  G11C16/34

CPC classification number: G11C16/3404 ,  A63B24/0075 ,  G11C16/26 ,  A63B2024/0068 ,  A63B2024/0093 ,  A63B2220/836 ,  A63B2230/06

Abstract: A memory system configured to dynamically adjust the amount of redundant information stored in memory cells of a wordline on an integrated circuit die based on a bit error rate. For example, in response to a determination that a bit error rate of the wordline is above a threshold, the memory system can store first data items as independent first codewords of an error correction code technique into a first portion of the memory cells of the wordline, generate second data items as redundant information from the first codewords, and store the second data items in a second portion of the memory cells of the wordline. If the bit error rate is below the threshold, third data items can be stored as independent second codewords of the same length as the first codewords in the memory cells of the wordline.

公开(公告)号：US20240071435A1

公开(公告)日：2024-02-29

申请号：US18198623

申请日：2023-05-17

Applicant: Micron Technology, Inc.

Inventor： Phong Sy Nguyen ,  Patrick R. Khayat ,  Jeffrey S. McNeil ,  Dung Viet Nguyen ,  Kishore Kumar Muchherla ,  James Fitzpatrick

IPC: G11C7/10

CPC classification number: G11C7/1069 ,  G11C7/1057 ,  G11C7/106

Abstract: Systems and methods are disclosed including a memory device comprising a memory array and control logic, operatively coupled with the memory array. The control logic can perform operations comprising causing a read operation to be initiated with respect to a set of target cells of the memory array; obtaining, for a respective group of adjacent cells, respective cell state information; performing a set of strobe reads on the set of target cells; and generating, for a target cell of the set of target cells, semi-soft bit data based on the respective cell state information of the respective group of adjacent cells and on data obtained from a first strobe read and a second strobe read of the set of strobe reads performed on the target cell.

公开(公告)号：US20240036973A1

公开(公告)日：2024-02-01

申请号：US17877637

申请日：2022-07-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Vamsi Pavan Rayaprolu ,  Dung Viet Nguyen ,  Zixiang Loh ,  Sampath K. Ratnam ,  Patrick R. Khayat ,  Thomas Herbert Lentz

IPC: G06F11/10

CPC classification number: G06F11/1044

Abstract: A request to access data programmed to a memory sub-system is received. A determination is made of whether memory cells of the memory sub-system that store the programmed data satisfy one or more cell degradation criteria. In response to a determination that the memory cells satisfy the one or more cell degradation criteria, an error correction operation to access the data is performed in accordance with the request.

公开(公告)号：US20230359388A1

公开(公告)日：2023-11-09

申请号：US17735458

申请日：2022-05-03

Applicant: Micron Technology, Inc.

Inventor： Dung Viet Nguyen ,  Patrick R. Khayat ,  Zhengang Chen ,  James Fitzpatrick ,  Sivagnanam Parthasarathy ,  Eric N. Lee

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: Described are systems and methods for memory read calibration based on memory device-originated metadata characterizing voltage distributions. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines; and a controller coupled to the memory array, the controller to perform operations comprising: receiving one or more metadata values characterizing threshold voltage distributions of a subset of the plurality of memory cells connected to one or more bitlines, wherein the one or more metadata values reflect a conductive state of the one or more bitlines; determining a read voltage adjustment value based on the one or more metadata values; and applying the read voltage adjustment value for reading the subset of the plurality of memory cells.