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公开(公告)号：US20230124024A1
公开(公告)日：2023-04-20
申请号：US17963790
申请日：2022-10-11
发明人： Robert B. Eisenhuth
IPC分类号： G06F3/06
摘要： Methods, systems, and devices for read threshold adjustment techniques for error recovery are described. A memory system may read a codeword from a memory array using one or more read thresholds. The memory system may increment one or more counters of the memory device based on reading the codeword. The one or more counters may indicate information related to how many bits of the codeword correspond to a particular logic value. The memory system may detect an error, such as an uncorrectable error, in the codeword based on reading the codeword. The memory system may adjust the one or more read thresholds based on the information indicated by the one or more counters and read the codeword using the adjusted read thresholds.
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公开(公告)号：US10355815B2
公开(公告)日：2019-07-16
申请号：US15160322
申请日：2016-05-20
发明人： Bruce A. Liikanen , Stephen P. Van Aken , Gerald L. Cadloni , John L. Seabury , Robert B. Eisenhuth
摘要： A system uses multi-level encoding where each symbol of a plurality of symbols represents more than one bit of information in a user data symbol stream for transfer using a multilevel transmission channel. The user data symbols are represented in a digital bitwise form such that each symbol is presented as a plurality of bits and each bit is subject to a different probability of error. An error correction procedure is applied based on the different error probability that is associated with each bit in the plurality. The channel can be configured to support a mosaic tile structure, each tile containing a channel symbol such that a selected tile has a collective error probability that is different from other tiles. Customized coding can be applied to the tile structure to allocate a selected amount of error correction power to the selected tile based on an overall available correction power.
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3.发明授权Advanced bitwise operations and apparatus in a multi-level system with nonvolatile memory 有权具有非易失性存储器的多级系统中的高级逐位操作和装置公开(公告)号：US09411675B2
公开(公告)日：2016-08-09
申请号：US14084497
申请日：2013-11-19
CPC分类号： G06F11/1012 , G06F11/10 , H03M13/1515 , H03M13/152 , H03M13/256 , H03M13/353 , H03M13/356 , H03M13/6362
摘要： A digital system, components and method are configured with nonvolatile memory for storing digital data using codewords. The data is stored in the memory using multiple bits per memory cell of the memory. A code efficiency, for purposes of write operations and read operations relating to the memory, can be changed on a codeword-to-codeword basis based on input parameters. The code efficiency can change based on changing any one of the input parameters including bit density that is stored by the memory. Storing and reading fractional bit densities can be performed.
摘要翻译： 数字系统，组件和方法被配置有非易失性存储器，用于使用码字存储数字数据。 数据存储在存储器中，每个存储器的每个存储单元使用多个位。 可以基于输入参数在码字到码字的基础上改变与存储器有关的写入操作和读取操作的代码效率。 代码效率可以根据改变任何一个输入参数而改变，包括由存储器存储的位密度。 可以执行存储和读取分数位密度。
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公开(公告)号：US20160094247A1
公开(公告)日：2016-03-31
申请号：US14502513
申请日：2014-09-30
发明人： Sivagnanam Parthasarathy , Nicholas Julian Richardson , Patrick Robert Khayat , Mustafa Nazmi Kaynak , Ka Leung Ling , Robert B. Eisenhuth
CPC分类号： H03M13/2927 , H03M13/1111 , H03M13/152 , H03M13/2906 , H03M13/3715
摘要： A memory device may include memory components to store data. The memory device may also include a processor that may decode a codeword associated with the data. The processor may receive the codeword and determine whether the codeword is independently decodable using a BCH decoder. The processor may then decode the codeword using the BCH decoder when the codeword is determined to be independently decodable using the BCH decoder. Otherwise, the processor may decode the codeword using a second decoder and the BCH decoder when the codeword is not determined to be independently decodable using the BCH decoder.
摘要翻译： 存储器设备可以包括用于存储数据的存储器组件。 存储器设备还可以包括可解码与数据相关联的码字的处理器。 处理器可以接收码字并且使用BCH解码器来确定码字是否可独立解码。 然后当使用BCH解码器确定码字可独立地解码时，处理器可以使用BCH解码器对码字进行解码。 否则，当码字未被确定为可以使用BCH解码器独立地解码时，处理器可以使用第二解码器和BCH解码器解码码字。
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5.发明申请ADVANCED BITWISE OPERATIONS AND APPARATUS IN A MULTI-LEVEL SYSTEM WITH NONVOLATILE MEMORY 有权具有非易失性存储器的多级系统中的先进的比特运算和设备公开(公告)号：US20140082454A1
公开(公告)日：2014-03-20
申请号：US14084497
申请日：2013-11-19
CPC分类号： G06F11/1012 , G06F11/10 , H03M13/1515 , H03M13/152 , H03M13/256 , H03M13/353 , H03M13/356 , H03M13/6362
摘要： A digital system, components and method are configured with nonvolatile memory for storing digital data using codewords. The data is stored in the memory using multiple bits per memory cell of the memory. A code efficiency, for purposes of write operations and read operations relating to the memory, can be changed on a codeword to codeword basis based on input parameters. The code efficiency can change based on changing any one of the input parameters including bit density that is stored by the memory. Storing and reading fractional bit densities is described.
摘要翻译： 数字系统，组件和方法被配置有非易失性存储器，用于使用码字存储数字数据。 数据存储在存储器中，每个存储器的每个存储单元使用多个位。 基于输入参数，可以在代码字到码字的基础上改变与存储器有关的写入操作和读取操作的代码效率。 代码效率可以根据改变任何一个输入参数而改变，包括由存储器存储的位密度。 描述存储和读取分数位密度。
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公开(公告)号：US20130332793A1
公开(公告)日：2013-12-12
申请号：US13966025
申请日：2013-08-13
IPC分类号： G06F11/07
CPC分类号： H04L7/0331 , G04F10/005 , G06F11/0793 , G11C11/4076 , G11C11/5642 , G11C29/02 , G11C29/12015 , G11C2211/5644 , H03M1/207 , H03M1/54
摘要： A counter configuration operates in cooperation with a delay configuration such that the counter configuration counts an input interval based on a given clock speed and a given clock interval while the delay configuration provides an enhanced data output that is greater than what would otherwise be provided by the given clock speed. The counter configuration counts responsive to a selected edge in the clock interval. An apparatus in the form of a correction arrangement and an associated method are configured to monitor at least the delay configuration output for detecting a particular time relationship between an endpoint of the input interval and a nearest occurrence of the selected clock edge in the given clock signal that is indicative of at least a potential error in the enhanced data output and determining if the potential error is an actual error for subsequent use in correcting the enhanced data output.
摘要翻译： 计数器配置与延迟配置协同工作，使得计数器配置基于给定的时钟速度和给定的时钟间隔对输入间隔进行计数，而延迟配置提供的增强数据输出大于由 给定时钟速度。 计数器配置响应于时钟间隔中的选定边沿计数。 校正装置和相关方法形式的装置被配置为至少监视延迟配置输出，用于检测输入间隔的端点与给定时钟信号中所选择的时钟沿的最近出现之间的特定时间关系 这表明增强数据输出中至少存在潜在的错误，并且确定潜在误差是否是后续用于校正增强数据输出的实际误差。
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公开(公告)号：US11450382B2
公开(公告)日：2022-09-20
申请号：US17074156
申请日：2020-10-19
摘要： A memory cell can have a state in a valley between adjacent data states. A determination can be made whether a state of a memory cell is in a valley between adjacent distributions of states associated with respective data states. A signal indicative of a data state of the memory cell and whether the state of the memory cell is in the valley can be transmitted.
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公开(公告)号：US11443828B1
公开(公告)日：2022-09-13
申请号：US17240938
申请日：2021-04-26
发明人： Robert B. Eisenhuth
摘要： Methods, systems, and devices for read threshold adjustment techniques for memory are described. A memory device may read a codeword from a memory array of the memory device using a read threshold having a first value. The memory device may increment one or more counters of the memory device based on reading the codeword. The counter may indicate a quantity of bits of the codeword that correspond to a first logic value. The memory device may detect an error, such as an uncorrectable error, in the codeword based on reading the codeword. The memory device may adjust the read threshold from the first value to the second value based on the quantity of bits indicated by the counter. The memory device may read the codeword using the read threshold having the second value.
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公开(公告)号：US11416393B2
公开(公告)日：2022-08-16
申请号：US17219727
申请日：2021-03-31
摘要： A method for performing a copyback procedure is described. The method includes determining to move first encoded data from a first location in a memory die to a second location. In response to determining to move the first encoded data from the first location to the second location, a starting seed, which is associated with the first location, is combined with a destination seed, which is associated with the second location, to produce a combined seed. Based on the combined seed, the method determines a pseudorandom sequence based on the combined seed and a pseudorandom sequence table, wherein the pseudorandom sequence table maps seed values to pseudorandom sequences and the determined pseudorandom sequence maps to the combined seed in the pseudorandom sequence table. The method further combines the first encoded data with the pseudorandom sequence to produce second encoded data for storage in the second location.
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公开(公告)号：US08782474B2
公开(公告)日：2014-07-15
申请号：US13966025
申请日：2013-08-13
CPC分类号： H04L7/0331 , G04F10/005 , G06F11/0793 , G11C11/4076 , G11C11/5642 , G11C29/02 , G11C29/12015 , G11C2211/5644 , H03M1/207 , H03M1/54
摘要： A counter configuration operates in cooperation with a delay configuration such that the counter configuration counts an input interval based on a given clock speed and a given clock interval while the delay configuration provides an enhanced data output that is greater than what would otherwise be provided by the given clock speed. The counter configuration counts responsive to a selected edge in the clock interval. An apparatus in the form of a correction arrangement and an associated method are configured to monitor at least the delay configuration output for detecting a particular time relationship between an endpoint of the input interval and a nearest occurrence of the selected clock edge in the given clock signal that is indicative of at least a potential error in the enhanced data output and determining if the potential error is an actual error for subsequent use in correcting the enhanced data output.
摘要翻译： 计数器配置与延迟配置协同工作，使得计数器配置基于给定的时钟速度和给定的时钟间隔对输入间隔进行计数，而延迟配置提供的增强数据输出大于由 给定时钟速度。 计数器配置响应于时钟间隔中的选定边沿计数。 校正装置和相关方法形式的装置被配置为至少监视延迟配置输出，用于检测输入间隔的端点与给定时钟信号中所选择的时钟沿的最近出现之间的特定时间关系 这表明增强数据输出中至少存在潜在的错误，并且确定潜在误差是否是后续用于校正增强数据输出的实际误差。
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