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    Adaptive Command Completion Timers
    2.
    发明公开
    Adaptive Command Completion Timers 审中-公开

    公开(公告)号：US20230205455A1

    公开(公告)日：2023-06-29

    申请号：US17561508

    申请日：2021-12-23

    Applicant: Micron Technology, Inc.

    Inventor： Karl D. Schuh ,  Daniel J. Hubbard

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0653 ,  G06F3/0604 ,  G06F3/0613 ,  G06F3/0679

    Abstract: Exemplary methods, apparatuses, and systems include receiving a request to perform an operation in memory. A subdivision of the memory to which the request is directed is determined. A command completion time based upon a command type for the operation and which subdivision of the memory to which the request is directed is determined. A command is sent to the memory for the operation. A request is sent to the memory for a status of the command based upon the determined command completion time.

    HANDLING BAD BLOCKS GENERATED DURING A BLOCK ERASE OPERATION
    5.
    发明申请
    HANDLING BAD BLOCKS GENERATED DURING A BLOCK ERASE OPERATION 有权

    公开(公告)号：US20210064267A1

    公开(公告)日：2021-03-04

    申请号：US16552750

    申请日：2019-08-27

    Applicant: Micron Technology, Inc.

    Inventor： Daniel J. Hubbard ,  Marc S. Hamilton ,  Kevin R. Brandt ,  William Akin

    IPC: G06F3/06

    Abstract: A memory component includes multiple fuses, a memory array having a multiple blocks, and control logic operatively coupled with the memory array and the plurality of fuses. The control logic is to receive an erase command associated with the memory array and attempt to erase, in response to receipt of the erase command, a block of the multiple blocks from the memory array. The control logic is further to detect a failure to completely erase the block. The control logic is further to receive a blow fuse command in response to the failure to completely erase the block. The control logic is to blow a fuse, of the multiple fuses, which is coupled with the block, to make the block of the multiple blocks inaccessible to the control logic.

    SPECIFYING MEDIA TYPE IN WRITE COMMANDS
    7.
    发明申请
    SPECIFYING MEDIA TYPE IN WRITE COMMANDS 审中-公开

    公开(公告)号：US20190303038A1

    公开(公告)日：2019-10-03

    申请号：US15937146

    申请日：2018-03-27

    Applicant: Micron Technology, Inc.

    Inventor： Daniel J. Hubbard

    IPC: G06F3/06

    Abstract: Systems and methods for specifying storage media types in write commands executable by storage devices are disclosed. An example system comprises: a plurality of memory devices and a controller operatively coupled to the memory devices, the controller configured to: receive a write command specifying a data item and an identifier of a data stream comprising the data item; determine, by parsing the identifier of the data stream, a data stream attribute shared by data items comprised by the data stream; identify, based on the data stream attribute, a memory device managed by the controller; and transmit, to the memory device, an instruction specifying the data item.

    Enhanced write performance utilizing program interleave
    8.
    发明授权
    Enhanced write performance utilizing program interleave 有权

    公开(公告)号：US12223208B2

    公开(公告)日：2025-02-11

    申请号：US18513742

    申请日：2023-11-20

    Applicant: Micron Technology, Inc.

    Inventor： Daniel J. Hubbard ,  Roy Leonard

    IPC: G06F3/06 ,  G06F12/0846 ,  G06F12/0882

    Abstract: A system includes a memory and a processing device, operatively coupled to the memory, to perform operations including initiating a write operation to write data to a first multiple level cell (XLC) storage including a first XLC block and a second XLC storage including a second XLC block, and causing a first portion of the data to be written to a first number of pages of the first XLC block and a second portion of the data to be written to a second number of pages of the second XLC block using page level interleave. The first number of pages and the second number of pages are defined by an interleave mix including an interleave ratio between a first XLC write mode and a second XLC write mode.

    BALANCING WEAR ACROSS MULTIPLE RECLAIM GROUPS
    9.
    发明申请
    BALANCING WEAR ACROSS MULTIPLE RECLAIM GROUPS 有权

    公开(公告)号：US20250013368A1

    公开(公告)日：2025-01-09

    申请号：US18747582

    申请日：2024-06-19

    Applicant: Micron Technology, Inc.

    Inventor： Daniel J. Hubbard ,  Meng Wei

    IPC: G06F3/06

    Abstract: Aspects of the present disclosure configure a memory sub-system controller to balance program-erase count (PEC) across multiple reclaim groups of a memory sub-system. The controller groups a set of memory components into a plurality of reclaim groups (RGs), each RG of the plurality of RGs comprising a subset of reclaim units (RUs). The controller receives a request to program a set of data into a first RG of the plurality of RGs and compares a first PEC of the first RG with a second PEC of a second RG of the plurality of RGs. The controller performs wear leveling operations for the set of data requested to be programmed into the first RG using one or more memory components associated with the second RG based on a result of comparing the first PEC of the first RG with the second PEC of the second RG.

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