公开(公告)号：US20240126690A1

公开(公告)日：2024-04-18

申请号：US18395363

申请日：2023-12-22

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Peter Feeley ,  Ashutosh Malshe ,  Daniel J. Hubbard ,  Christopher S. Hale ,  Kevin R. Brandt ,  Sampath K. Ratnam ,  Yun Li ,  Marc S. Hamilton

IPC: G06F12/02 ,  G06F3/06 ,  G06F12/00 ,  G06F12/06 ,  G06F12/0891

CPC classification number: G06F12/0253 ,  G06F3/0629 ,  G06F3/0634 ,  G06F3/064 ,  G06F3/0688 ,  G06F3/0689 ,  G06F12/00 ,  G06F12/0646 ,  G06F12/0891 ,  G11C11/5621

Abstract: A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: designate a storage mode for a target set of memory cells based on valid data in a source block, wherein the target set of memory cells are configured with a capacity to store up to a maximum number of bits per cell, and the storage mode is for dynamically configuring the target set of memory cells in as cache memory that stores a number of bits less per cell than the corresponding maximum capacity.

公开(公告)号：US11688483B2

公开(公告)日：2023-06-27

申请号：US17521785

申请日：2021-11-08

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Sampath K. Ratnam ,  Scott A. Stoller ,  Preston A. Thomson ,  Kevin R. Brandt ,  Marc S. Hamilton ,  Christopher S. Hale

IPC: G11C29/00 ,  G11C29/38 ,  G11C29/44

CPC classification number: G11C29/38 ,  G11C29/44

Abstract: A processing device in a memory system detects a data loss occurrence in a block of a memory component. The processing device further designates the block as a quarantined block, performs a stress test on the block, and depending on whether the stress test on the block satisfies a testing criterion, either designates the block as usable by the memory component or retires the block of the memory component.

公开(公告)号：US11106577B2

公开(公告)日：2021-08-31

申请号：US16175005

申请日：2018-10-30

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Peter Sean Feeley ,  Sampath K. Ratnam ,  Ashutosh Malshe ,  Christopher S. Hale

IPC: G06F12/128 ,  G06F12/02 ,  G06F12/0897

Abstract: An amount of valid data for each data block of multiple data blocks stored at a first memory is determined. An operation to write valid data of a particular data block from the first memory to a second memory is performed based on the amount of valid data for each data block. A determination is made that a threshold condition associated with when valid data of the data blocks was written to the first memory has been satisfied. In response to determining that the threshold condition has been satisfied, the operation to write valid data of the data blocks from the first memory to the second memory is performed based on when the valid data was written to the first memory.

公开(公告)号：US20210191858A1

公开(公告)日：2021-06-24

申请号：US17196934

申请日：2021-03-09

Applicant: Micron Technology, Inc.

Inventor： Yun Li ,  Kishore Kumar Muchherla ,  Peter Feeley ,  Ashutosh Malshe ,  Daniel J. Hubbard ,  Christopher S. Hale ,  Kevin R. Brandt ,  Sampath K. Ratnam

IPC: G06F12/02 ,  G06F12/0891

Abstract: Memory circuits including dynamically configurable cache cells are disclosed herein. The cache cells may be selectively and dynamically configured to select one or more bits per cell according to a real-time determination or characterization of a workload type.

公开(公告)号：US20210118519A1

公开(公告)日：2021-04-22

申请号：US16660483

申请日：2019-10-22

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Sampath K. Ratnam ,  Scott A. Stoller ,  Preston A. Thomson ,  Kevin R. Brandt ,  Marc S. Hamilton ,  Christopher S. Hale

IPC: G11C29/38 ,  G11C29/44

Abstract: A processing device in a memory system detects a data loss occurrence in a block of a memory component. The processing device identifies a behavioral criterion associated with the data loss occurrence in the block of the memory component. The processing device further increments a counter associated with the block in response to an occurrence of the behavioral criterion, wherein a value of the counter corresponds to a number of occurrences of a plurality of behavioral criteria associated with data loss occurrences in the block. Responsive to determining that the value of the counter satisfies a first threshold criterion, the processing device designates the block as a quarantined block, performs a stress test of a plurality of stress tests of the block, and responsive to the block failing a first stress test, the processing device retires the block of the memory component.

公开(公告)号：US12216573B2

公开(公告)日：2025-02-04

申请号：US18395363

申请日：2023-12-22

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Peter Feeley ,  Ashutosh Malshe ,  Daniel J. Hubbard ,  Christopher S. Hale ,  Kevin R. Brandt ,  Sampath K. Ratnam ,  Yun Li ,  Marc S. Hamilton

IPC: G06F3/00 ,  G06F3/06 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0891 ,  G11C11/56

Abstract: A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: designate a storage mode for a target set of memory cells based on valid data in a source block, wherein the target set of memory cells are configured with a capacity to store up to a maximum number of bits per cell, and the storage mode is for dynamically configuring the target set of memory cells in as cache memory that stores a number of bits less per cell than the corresponding maximum capacity.

公开(公告)号：US11720493B2

公开(公告)日：2023-08-08

申请号：US17581108

申请日：2022-01-21

Applicant: Micron Technology, Inc.

Inventor： Kevin R. Brandt ,  Peter Feeley ,  Kishore Kumar Muchherla ,  Yun Li ,  Sampath K. Ratnam ,  Ashutosh Malshe ,  Christopher S. Hale ,  Daniel J. Hubbard

IPC: G06F12/08 ,  G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/60

Abstract: System and methods are disclosed include a memory device and a processing device coupled to the memory device. The processing device can determine an amount of valid management units in a memory device of a memory sub-system. The processing device can then determine a surplus amount of valid management units on the memory device based on the amount of valid management units. The processing device can then configure a size of a cache of the memory device based on the surplus amount of valid management units.

公开(公告)号：US11593261B2

公开(公告)日：2023-02-28

申请号：US17374906

申请日：2021-07-13

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Peter Feeley ,  Ashutosh Malshe ,  Daniel J. Hubbard ,  Christopher S. Hale ,  Kevin R. Brandt ,  Sampath K. Ratnam ,  Yun Li ,  Marc S. Hamilton

IPC: G06F12/00 ,  G06F12/02 ,  G06F12/0891 ,  G06F3/06 ,  G06F12/06 ,  G11C11/56

Abstract: A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: designate a storage mode for a target set of memory cells based on valid data in a source block, wherein the target set of memory cells are configured with a capacity to store up to a maximum number of bits per cell, and the storage mode is for dynamically configuring the target set of memory cells in as cache memory that stores a number of bits less per cell than the corresponding maximum capacity.

公开(公告)号：US20220068422A1

公开(公告)日：2022-03-03

申请号：US17521785

申请日：2021-11-08

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Sampath K. Ratnam ,  Scott A. Stoller ,  Preston A. Thomson ,  Kevin R. Brandt ,  Marc S. Hamilton ,  Christopher S. Hale

IPC: G11C29/38 ,  G11C29/44

Abstract: A processing device in a memory system detects a data loss occurrence in a block of a memory component. The processing device further designates the block as a quarantined block, performs a stress test on the block, and depending on whether the stress test on the block satisfies a testing criterion, either designates the block as usable by the memory component or retires the block of the memory component.

公开(公告)号：US20180373639A1

公开(公告)日：2018-12-27

申请号：US16118901

申请日：2018-08-31

Applicant: Micron Technology, Inc.

Inventor： Christopher S. Hale ,  Sampath K. Ratnam ,  Kishore K. Muchherla

IPC: G06F12/0897 ,  G06F12/02 ,  G06F3/06 ,  G06F12/0871 ,  G06F12/0804

Abstract: The present disclosure includes memory having a static cache and a dynamic cache. A number of embodiments include a memory, wherein the memory includes a first portion configured to operate as a static single level cell (SLC) cache and a second portion configured to operate as a dynamic SLC cache when the entire first portion of the memory has data stored therein.