公开(公告)号：US20240378145A1

公开(公告)日：2024-11-14

申请号：US18641286

申请日：2024-04-19

Applicant: Micron Technology, Inc.

Inventor： Jonathan R. Hinkle ,  Luca Bert

IPC: G06F12/02

Abstract: Methods, apparatuses, and systems related to serially chained memory subsystems are described. The grouped set of chained subsystems may coordinate internal communications and operations across the separate subsystems within the set. Memory locations for related or connected data may be dynamically computed to be across multiple subsystems to allow for parallel processing, failure/error recovery, or the like.

公开(公告)号：US12086432B2

公开(公告)日：2024-09-10

申请号：US17591554

申请日：2022-02-02

Applicant: Micron Technology, Inc.

Inventor： Luca Bert ,  Joseph Harold Steinmetz

IPC: G06F3/06

CPC classification number: G06F3/0631 ,  G06F3/0608 ,  G06F3/0634 ,  G06F3/0659 ,  G06F3/0679

Abstract: An apparatus with a solid state drive (SSD) configured to manage storage resources for proof of space activities. The SSD has a host interface configured to receive at least read commands and write commands from an external host system. The SSD has memory cells formed on at least one integrated circuit die, and a processing device configured to control executions of the read commands and the write commands. In response to an indication of a storage space request for the host system, the apparatus identifies a portion of storage resources used to store the data of the proof of space plot, and reallocates the portion to service the host system. Subsequently, the SSD can continue proof of space activities based on the proof of space plot using the data stored in a remaining portion of the storage resources initially allocated to the proof of space plot.

公开(公告)号：US20240231708A1

公开(公告)日：2024-07-11

申请号：US18613950

申请日：2024-03-22

Applicant: Micron Technology, Inc.

Inventor： Luca Bert

IPC: G06F3/06 ,  G06F11/10

CPC classification number: G06F3/0689 ,  G06F3/0604 ,  G06F3/0655 ,  G06F11/1032 ,  G06F11/1076 ,  G06F11/108

Abstract: Aspects of the present disclosure configure a system component, such as memory sub-system controller, to dynamically generate Redundant Array of Independent Nodes (RAIN) parity information for zone-based memory allocations. The RAIN parity information is generated for a given zone or set of zones on the basis of whether the given zone or set of zones satisfy a zone completeness criterion. The zone completeness criterion can represent a specified size such that when a given zone reaches the specified size, the parity information for that zone is generated.

公开(公告)号：US20240220132A1

公开(公告)日：2024-07-04

申请号：US18608114

申请日：2024-03-18

Applicant: Micron Technology, Inc.

Inventor： Joseph Harold Steinmetz ,  Luca Bert

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0653 ,  G06F3/0673

Abstract: A memory sub-system, such as a solid-state drive (SSD), having host interface configured to receive at least read commands and write commands from an external host system. The SSD has memory cells formed on at least one integrated circuit die, and a processing device configured to control executions of the read commands to retrieve data from the memory cells and executions the write commands to store data into the memory cells. During an autonomous self-test operation of the memory sub-system, the memory sub-system is configured to generate random challenges of proof of space, generate using a proof of space plot, stored in the memory cells, responses to the random challenges respectively, and determine validity of the responses to evaluate health of the memory cells.

公开(公告)号：US20240143422A1

公开(公告)日：2024-05-02

申请号：US18392457

申请日：2023-12-21

Applicant: Micron Technology, Inc.

Inventor： Luca Bert

IPC: G06F9/54 ,  G06F13/16

CPC classification number: G06F9/546 ,  G06F13/1668

Abstract: A storage product having: a network interface operable on a computer network; a bus connector adapted to be connected to a computer bus; a storage device having a storage capacity accessible through network storage services provided over the network interface; and a processing device configured to at least generate storage access messages from incoming packets received by the network interface from the computer network. The storage product is operable in a standalone mode when no local host system is connected to the bus connector to control the storage product and operable in a slave mode when a local host system is connected to the bus connector to process a portion of the storage access messages.

公开(公告)号：US20240028546A1

公开(公告)日：2024-01-25

申请号：US18481047

申请日：2023-10-04

Applicant: Micron Technology, Inc.

Inventor： Luca Bert

IPC: G06F13/40 ,  G06F13/16

CPC classification number: G06F13/409 ,  G06F13/4022 ,  G06F13/1668

Abstract: A storage product manufactured as a computer component to facilitate network storage services. The storage product has no central processing unit. The storage product has a bus connector connectable to a computer bus. An external processor connected to the computer bus can operate as a central processing unit. The storage product has a random-access memory, a network interface, a processing device, and a storage device having a storage capacity accessible via the network interface. The bus connector provides the processor with access to the random-access memory. The processing device of the storage product can identify and separate, among messages received by the network interface, first messages for processing by the external processor and second messages for processing by the storage device.

公开(公告)号：US20240022526A1

公开(公告)日：2024-01-18

申请号：US17866318

申请日：2022-07-15

Applicant: Micron Technology, Inc.

Inventor： Luca Bert

IPC: H04L49/00 ,  H04L49/103 ,  H04L49/90 ,  H04L67/1097

CPC classification number: H04L49/3036 ,  H04L49/103 ,  H04L49/9036 ,  H04L67/1097

Abstract: A memory sub-system connectable to a microprocessor to provide network storage services. The memory sub-system has a random-access memory configured with: first queues for the microprocessor and a network interface; second queues for the microprocessor and a processing device; and third queues for the processing device and a storage device. The processing device is configured to: generate first control messages and first data messages from packets received by the network interface; place the first control messages into the first queues for the microprocessor; and place the first data messages into the third queues for the storage device. The microprocessor processes the first control messages to implement security and administrative functions and place second control messages in the second queues. The storage device is configured to retrieve the first data messages from the third queues and second control messages from the second queues for processing.

公开(公告)号：US20240020051A1

公开(公告)日：2024-01-18

申请号：US17866300

申请日：2022-07-15

Applicant: Micron Technology, Inc.

Inventor： Luca Bert

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/0659 ,  G06F3/067 ,  G06F3/0622

Abstract: A method to provide network storage services to a remote host system, including: generating, from packets received from the remote host system, first control messages and first data messages; buffering, in a random-access memory of a memory sub-system, the first control messages for a local host system to fetch the first control messages, process the first control messages, and generate second control messages; sending the first data messages to a storage device of the memory sub-system without the first data messages being buffered in the random-access memory; communicating the second control messages generated by the local host system to the storage device of the memory sub-system; and processing, within the storage device, the second control messages and the first data messages to provide the network storage services.

公开(公告)号：US11868828B1

公开(公告)日：2024-01-09

申请号：US17866357

申请日：2022-07-15

Applicant: Micron Technology, Inc.

Inventor： Luca Bert

IPC: G06F9/54 ,  G06F13/16

CPC classification number: G06F9/546 ,  G06F13/1668

Abstract: A storage product having a network interface and a bus switch connecting a random-access memory, a processing device, and a storage device, and connected via an external computer bus to an external processor. The storage product can receive via the network interface first messages and second messages for network storage services. The bus switch is operable to provide a first bus between the processing device and the random-access memory to buffer the first messages into the random-access memory, a second bus between the processing device and the storage device to buffer the second messages into a local memory of the storage device, and a third bus between the processor and the random-access memory to retrieve the first messages from the random-access memory and generate third messages. The storage device is configured to process the second and third messages to provide network storage services.

公开(公告)号：US11868827B1

公开(公告)日：2024-01-09

申请号：US17866350

申请日：2022-07-15

Applicant: Micron Technology, Inc.

Inventor： Luca Bert

IPC: G06F9/54 ,  G06F13/16

CPC classification number: G06F9/546 ,  G06F13/1668

Abstract: A storage product having: a network interface operable on a computer network; a bus connector adapted to be connected to a computer bus; a storage device having a storage capacity accessible through network storage services provided over the network interface; and a processing device configured to at least generate storage access messages from incoming packets received by the network interface from the computer network. The storage product is operable in a standalone mode when no local host system is connected to the bus connector to control the storage product and operable in a slave mode when a local host system is connected to the bus connector to process a portion of the storage access messages.