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公开(公告)号：US20240281324A1
公开(公告)日：2024-08-22
申请号：US18443011
申请日：2024-02-15
Applicant: Micron Technology, Inc.
Inventor： Deping He , Caixia Yang
CPC classification number: G06F11/1064 , G06F11/076 , G06F11/1016
Abstract: Methods, systems, and devices for critical data management within a memory system are described. A memory system may avoid writing critical data to weak word lines. For example, as part of a media management operation or a host write operation (among other examples), the memory system may determine which data is critical data and may determine which word lines are weak word lines, which may refer to word lines having bit error rates that satisfy a threshold. The memory system may refrain from writing critical data to memory cells coupled with weak word lines, and may instead write non-critical or dummy data to the weak word lines. The memory system may reserve the writing of critical data to memory cells coupled with non-weak word lines, which may refer to word lines having bit error rates that fail to satisfy the threshold.
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公开(公告)号：US20240241663A1
公开(公告)日：2024-07-18
申请号：US18417808
申请日：2024-01-19
Applicant: Micron Technology, Inc.
Inventor： Caixia Yang , Deping He
IPC: G06F3/06
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0676 , G06F3/0679
Abstract: Methods, systems, and devices for suspension during a multi-plane write procedure are described. A memory system may perform a multi-plane write procedure by writing to a set of planes in parallel. Upon detecting a defective plane in the set of planes, the memory system may suspend writing to the defective plane until writing to the other planes in the set of planes is finished. The memory system may then resume writing to the defective plane.
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公开(公告)号：US20230418491A1
公开(公告)日：2023-12-28
申请号：US17846761
申请日：2022-06-22
Applicant: Micron Technology, Inc.
Inventor： Deping He , Bo Zhou , Caixia Yang
IPC: G06F3/06
CPC classification number: G06F3/064 , G06F3/061 , G06F3/0679
Abstract: Methods, systems, and devices for memory block utilization in memory systems are described. A system configured to allow a memory device to group or segment a memory block into two or more sub-memory blocks, which can be independently programmed is described herein. For example, a host system may determine a configuration of a memory array, and communicate the configuration information to the memory system, and transmit a command for an operation to the memory system. In some examples, the memory system may utilize the memory array configuration information and determine to segment the blocks of memory cells into sub-blocks. By segmenting the memory block into sub-blocks, the memory device may maintain its memory block density while supporting efficient programming of blocks of the memory array.
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公开(公告)号：US20230375353A1
公开(公告)日：2023-11-23
申请号：US17748149
申请日：2022-05-19
Applicant: Micron Technology, Inc.
Inventor： Linh H. Nguyen , Barbara J. Bailey , Caixia Yang
CPC classification number: G01C21/3484 , G01C21/3629 , A61B34/25 , A61B2034/252
Abstract: Apparatuses, media, and methods associated with providing guidance while performing tasks are described. Guidance can be provided in the form of directions for reaching a destination. For example, the guidance can include determining a destination and/or providing directions to reach the destination in the least amount of time. The guidance can include directions in the form of audible turn by turn instructions, a route shown on a map, and/or indications by streetlights or street signs (e.g., the route to the destination is indicated by flashing streetlights or words shown on street signs), among other types of guidance. Guidance can be provided in the form of instructions for performing a task. For example, the guidance can include instructions for treating a medical condition of an individual in an ambulance.
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公开(公告)号：US20240319899A1
公开(公告)日：2024-09-26
申请号：US18634584
申请日：2024-04-12
Applicant: Micron Technology, Inc.
Inventor： Deping He , Caixia Yang
IPC: G06F3/06
CPC classification number: G06F3/064 , G06F3/0619 , G06F3/0667 , G06F3/0673
Abstract: Methods, systems, and devices for assigning blocks of memory systems are described. Some memory systems may be configured to initiate an operation to characterize a plurality of blocks of a memory system; identify a first quantity of complete blocks of the plurality of blocks and a second quantity of reduced blocks of the plurality of blocks based at least in part on initiating the operation; determine, for a block of the second quantity of reduced blocks, whether a quantity of planes available for use to store the information in the block satisfies a threshold; and assign the block as a special function block configured to store data associated with a function of the memory system based at least in part on determining that the quantity of planes available for use to store the information in the block of the second quantity of reduced blocks satisfies the threshold.
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公开(公告)号：US11977758B2
公开(公告)日：2024-05-07
申请号：US17887247
申请日：2022-08-12
Applicant: Micron Technology, Inc.
Inventor： Deping He , Caixia Yang
IPC: G06F3/06
CPC classification number: G06F3/064 , G06F3/0619 , G06F3/0667 , G06F3/0673
Abstract: Methods, systems, and devices for assigning blocks of memory systems are described. Some memory systems may be configured to initiate an operation to characterize a plurality of blocks of a memory system; identify a first quantity of complete blocks of the plurality of blocks and a second quantity of reduced blocks of the plurality of blocks based at least in part on initiating the operation; determine, for a block of the second quantity of reduced blocks, whether a quantity of planes available for use to store the information in the block satisfies a threshold; and assign the block as a special function block configured to store data associated with a function of the memory system based at least in part on determining that the quantity of planes available for use to store the information in the block of the second quantity of reduced blocks satisfies the threshold.
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公开(公告)号：US20240053911A1
公开(公告)日：2024-02-15
申请号：US17887247
申请日：2022-08-12
Applicant: Micron Technology, Inc.
Inventor： Deping He , Caixia Yang
IPC: G06F3/06
CPC classification number: G06F3/064 , G06F3/0667 , G06F3/0619 , G06F3/0673
Abstract: Methods, systems, and devices for assigning blocks of memory systems are described. Some memory systems may be configured to initiate an operation to characterize a plurality of blocks of a memory system; identify a first quantity of complete blocks of the plurality of blocks and a second quantity of reduced blocks of the plurality of blocks based at least in part on initiating the operation; determine, for a block of the second quantity of reduced blocks, whether a quantity of planes available for use to store the information in the block satisfies a threshold; and assign the block as a special function block configured to store data associated with a function of the memory system based at least in part on determining that the quantity of planes available for use to store the information in the block of the second quantity of reduced blocks satisfies the threshold.
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公开(公告)号：US11899963B2
公开(公告)日：2024-02-13
申请号：US17654552
申请日：2022-03-11
Applicant: Micron Technology, Inc.
Inventor： Caixia Yang , Deping He
IPC: G06F3/06
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0676 , G06F3/0679
Abstract: Methods, systems, and devices for suspension during a multi-plane write procedure are described. A memory system may perform a multi-plane write procedure by writing to a set of planes in parallel. Upon detecting a defective plane in the set of planes, the memory system may suspend writing to the defective plane until writing to the other planes in the set of planes is finished. The memory system may then resume writing to the defective plane.
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公开(公告)号：US20230289088A1
公开(公告)日：2023-09-14
申请号：US17654552
申请日：2022-03-11
Applicant: Micron Technology, Inc.
Inventor： Caixia Yang , Deping He
IPC: G06F3/06
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0679 , G06F3/0676
Abstract: Methods, systems, and devices for suspension during a multi-plane write procedure are described. A memory system may perform a multi-plane write procedure by writing to a set of planes in parallel. Upon detecting a defective plane in the set of planes, the memory system may suspend writing to the defective plane until writing to the other planes in the set of planes is finished. The memory system may then resume writing to the defective plane.
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10.发明申请
公开(公告)号：US20240393977A1
公开(公告)日：2024-11-28
申请号：US18636584
申请日：2024-04-16
Applicant: Micron Technology, Inc.
Inventor： Ratna Priyanka Sistla , Dan Xu , Tomoko Ogura Iwasaki , Caixia Yang , Lee-eun Yu
IPC: G06F3/06
Abstract: A memory device includes a memory array configured as quad-level cell (QLC) memory and a control logic operatively coupled to the memory array. The control logic identifies a first two bits of particular pages of a QLC logical state. The control logic causes memory cells of the memory array to be coarse programmed with a threshold voltage distribution of a multi-level cell (MLC) logical state corresponding to the first two bits. The control logic reads the MLC logical state from the memory cells and a second two bits from a cache buffer to determine the QLC logical state. The control logic causes the memory cells to be further coarse programmed with a QLC threshold voltage distribution corresponding to the QLC logical state.
