Invention Publication
- Patent Title: MANAGING SUB-BLOCK ERASE OPERATIONS IN A MEMORY SUB-SYSTEM
-
Application No.: US18224179Application Date: 2023-07-20
-
Publication No.: US20230360709A1Publication Date: 2023-11-09
- Inventor: Kalyan Chakravarthy Kavalipurapu , Tomoko Ogura Iwasaki , Erwin E. Yu , Hong-Yan Chen , Yunfei Xu
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Main IPC: G11C16/16
- IPC: G11C16/16 ; G06F3/06 ; G11C16/04 ; G11C16/08

Abstract:
A processing device in a memory system connects a first data block of the memory device to a second data block of the memory device to generate a combined data block comprising a first plurality of sub-blocks of the first data block and a second plurality of sub-blocks of the second data block, wherein the connecting includes: for each wordline of a first plurality of wordlines of the first data block, creating a wordline connection short between the respective wordline of the first data block and a corresponding wordline of a second plurality of wordlines of the second data block, wherein the first plurality of wordlines and the second plurality of wordlines comprise data wordlines; and driving a first data wordline of the first data block and a second wordline of the second data block using a single string driver of the memory device.
Public/Granted literature
- US12068037B2 Managing sub-block erase operations in a memory sub-system Public/Granted day:2024-08-20
Information query