Control logic in a memory device identifies memory cells of a memory array configured as single-level cell (SLC) memory, where the memory cells include two or more memory cells programmed during a program phase and associated with a selected wordline of the memory array. The control logic further causes a program verify voltage to be applied to the selected wordline during a ganged SLC verify operation to be performed concurrently on the memory cells. In response to the memory cells failing to pass ganged SLC verify operation, the control logic further: copies first data, which is associated with a first memory cell, into the data recovery latch; causes a program verify operation to be performed separately on the first memory cell; and in response to the first memory cell reaching a program verify voltage, causes an inhibit of the first memory cell from further programming.