公开(公告)号：US12165710B2

公开(公告)日：2024-12-10

申请号：US17591516

申请日：2022-02-02

Applicant: Micron Technology, Inc.

Inventor： Koichi Kawai ,  Yoshihiko Kamata

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/34

Abstract: A memory device includes a sense amplifier (SA) latch coupled to a sense node. A dynamic latch (DL) is connected to the SA latch and coupled to sense node. A sense line includes the sense node and is selectively connected to the SA latch, the DL, and a bit line that is coupled to a memory cell string. Control logic is coupled to the SA latch and the DL, and to: cause a pre-program verify voltage to boost the sense node; and, in response to detecting a high bit value stored in SA latch, cause a voltage to turn on set transistor(s) of DL so that a first bias voltage or a second bias voltage is stored at a latch transistor. The first bias voltage is useable for slow programming of a selected memory cell and the second bias voltage is useable for fast programming of the selected memory cell.

公开(公告)号：US11915758B2

公开(公告)日：2024-02-27

申请号：US18095049

申请日：2023-01-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hao T. Nguyen ,  Tomoko Ogura Iwasaki ,  Erwin E. Yu ,  Dheeraj Srinivasan ,  Sheyang Ning ,  Lawrence Celso Miranda ,  Aaron S. Yip ,  Yoshihiko Kamata

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C11/56

CPC classification number: G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3459 ,  G11C11/5621 ,  G11C11/5671

Abstract: Memory devices might include a first storage element, a second storage element, a data line, and a controller. The first storage element is to store a first data bit. The second storage element is to store a second data bit. The data line is selectively connected to the first storage element, the second storage element, and a memory cell. The controller is configured to apply one of four voltage levels to the data line based on the first data bit and the second data bit.

公开(公告)号：US11562791B1

公开(公告)日：2023-01-24

申请号：US17396825

申请日：2021-08-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hao T. Nguyen ,  Tomoko Ogura Iwasaki ,  Erwin E. Yu ,  Dheeraj Srinivasan ,  Sheyang Ning ,  Lawrence Celso Miranda ,  Aaron S. Yip ,  Yoshihiko Kamata

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  G11C16/26 ,  G11C11/56

Abstract: Memory devices might include a first latch to store a first data bit; a second latch to store a second data bit; a data line selectively connected to the first latch, the second latch, and a string of series-connected memory cells; and a controller configured to bias the data line during a programing operation of a selected memory cell. The controller may with the first data bit equal to 0 and the second data bit equal to 0, bias the data line to a first voltage level; with the first data bit equal to 1 and the second data bit equal to 0, bias the data line to a second voltage level; with the first data bit equal to 0 and the second data bit equal to 1, bias the data line to a third voltage level; and with the first data bit equal to 1 and the second data bit equal to 1, bias the data line to a fourth voltage level.

公开(公告)号：US20220301634A1

公开(公告)日：2022-09-22

申请号：US17203830

申请日：2021-03-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshihiko Kamata

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/30

Abstract: Memory devices might include a capacitor, a first capacitance element, a first transistor, and control logic. The first transistor might be connected between the capacitor and the first capacitance element. The control logic might be connected to a control gate of the first transistor. The control logic might be configured to activate the first transistor to precharge the capacitor and the first capacitance element during a read operation of the memory device. The first capacitance element might be a wire capacitance of a first signal line.

公开(公告)号：US20220199176A1

公开(公告)日：2022-06-23

申请号：US17463645

申请日：2021-09-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshihiko Kamata

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10

Abstract: Memory devices might include an array of memory cells including a plurality of strings of series-connected memory cells, a plurality of access lines, a common source, a plurality of data lines, a plurality of shield lines, and control logic. Each access line might be connected to a control gate of a respective memory cell of each string of series-connected memory cells. Each string of series-connected memory cells might be selectively connected between the common source and a respective data line. The plurality of shield lines might be interleaved with the plurality of data lines. The control logic might be configured to implement a program verify operation of respective memory cells coupled to a selected access line including sensing a voltage level on each data line to determine whether each respective memory cell coupled to the selected access line has been programmed to a target level for the respective memory cell.

公开(公告)号：US20220181254A1

公开(公告)日：2022-06-09

申请号：US17681377

申请日：2022-02-25

Applicant: Micron Technology, Inc.

Inventor： Naveen Kaushik ,  Yoshihiko Kamata ,  Richard J. Hill ,  Kyle A. Ritter ,  Tomoko Ogura Iwasaki ,  Haitao Liu

IPC: H01L23/522 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11556

Abstract: Some embodiments include an assembly having channel-material-structures, and having memory cells along the channel-material-structures. The memory cells include charge-storage-material. Linear-conductive-structures are vertically offset from the channel-material-structures and are electrically coupled with the channel-material-structures. Intervening regions are between the linear-conductive-structures. Conductive-shield-structures are within the intervening regions. The conductive-shield-structures are electrically coupled with a reference-voltage-source.

公开(公告)号：US20220068953A1

公开(公告)日：2022-03-03

申请号：US17006364

申请日：2020-08-28

Applicant: Micron Technology, Inc.

Inventor： Koichi Kawai ,  Yoshihiko Kamata ,  Yoshiaki Fukuzumi ,  Tamotsu Murakoshi

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/02 ,  G11C16/24 ,  G11C16/04

Abstract: A microelectronic device comprises first digit lines, second digit lines, and multiplexer devices. The first digit lines are coupled to strings of memory cells. The second digit lines are coupled to additional strings of memory cells. The second digit lines are offset from the first digit lines in a first horizontal direction and are substantially aligned with the first digit lines in a second horizontal direction orthogonal to the first horizontal direction. The multiplexer devices are horizontally interposed between the first digit lines and the second digit lines in the first horizontal direction. The multiplexer devices are in electrical communication with the first digit lines, the second digit lines, and page buffer devices. Additional microelectronic devices, memory devices, and electronic systems are also described.

公开(公告)号：US20240071507A1

公开(公告)日：2024-02-29

申请号：US17894248

申请日：2022-08-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Koichi Kawai ,  Yoshihiko Kamata ,  Akira Goda

IPC: G11C16/10 ,  G11C7/10 ,  G11C16/34 ,  H03K19/017

CPC classification number: G11C16/102 ,  G11C7/1048 ,  G11C16/3459 ,  H03K19/01742

Abstract: Memories might include a controller configured to cause the memory to apply a first voltage level indicative of a data state of a memory cell of an array of memory cells to a control gate of a transistor, retain the first voltage level on the control gate of the transistor, connect a first source/drain of the transistor to a data line corresponding to the memory cell while applying a second voltage level to a second source/drain of the transistor and while retaining the first voltage level on the control gate of the transistor, and apply a programming pulse to a control gate of the memory cell while the data line is connected to the first source/drain of the transistor.

公开(公告)号：US11823752B2

公开(公告)日：2023-11-21

申请号：US18095711

申请日：2023-01-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshihiko Kamata

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/10

CPC classification number: G11C16/3459 ,  G11C16/0483 ,  G11C16/10

Abstract: Memory devices might include an array of memory cells, a plurality of access lines connected to the array of memory cells, a plurality of data lines connected to the array of memory cells, a plurality of shield lines, and control logic. The plurality of shield lines might be interleaved with the plurality of data lines. The control logic might be configured to implement a program verify operation of respective memory cells of the array of memory cells connected to a selected access line including charging the plurality of shield lines to a first voltage level, discharging the plurality of shield lines to a voltage level less than the first voltage level, and sensing a voltage level on each data line to determine whether each respective memory cell coupled to the selected access line has been programmed to a target level for the respective memory cell.

公开(公告)号：US11386966B2

公开(公告)日：2022-07-12

申请号：US17111770

申请日：2020-12-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshiaki Fukuzumi ,  Jun Fujiki ,  Shuji Tanaka ,  Masashi Yoshida ,  Masanobu Saito ,  Yoshihiko Kamata

IPC: G11C11/34 ,  G11C16/26 ,  G11C16/04 ,  G11C16/10 ,  G11C11/56 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11556

Abstract: Memory might include a non-volatile memory cell, a capacitance selectively connected to the non-volatile memory cell, a field-effect transistor having a channel capacitively coupled to an electrode of the capacitance, and a controller for access of the non-volatile memory cell configured to cause the memory to increase a voltage level of the electrode of the capacitance, selectively discharge the voltage level of the electrode of the capacitance through the non-volatile memory cell responsive to a data state stored in the non-volatile memory cell, and determine whether the field-effect transistor is activated in response to a remaining voltage level of the electrode of the capacitance.