公开(公告)号：US20240412790A1

公开(公告)日：2024-12-12

申请号：US18806931

申请日：2024-08-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshiaki Fukuzumi ,  Jun Fujiki ,  Shuji Tanaka ,  Masashi Yoshida ,  Masanobu Saito ,  Yoshihiko Kamata

IPC: G11C16/26 ,  G11C16/04

Abstract: Apparatus might include a plurality of series-connected first field-effect transistors selectively connected in series with a plurality of series-connected second field-effect transistors, wherein the plurality of series-connected first field-effect transistors are configured to store user data, and wherein a channel of the plurality of series-connected second transistors is capacitively coupled to a channel of a third transistor.

公开(公告)号：US20240074201A1

公开(公告)日：2024-02-29

申请号：US17893436

申请日：2022-08-23

Applicant: Micron Technology, Inc.

Inventor： Matthew J. King ,  Albert Fayrushin ,  Sidhartha Gupta ,  Jun Fujiki ,  Masashi Yoshida ,  Yiping Wang ,  Taehyun Kim ,  Arun Kumar Dhayalan

IPC: H01L27/1157 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L27/1157 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11582

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating different-composition first tiers and second tiers. The stack comprises lower channel-material strings extending through the first tiers and the second tiers. Conductive masses are formed that comprise at least one of conductively-doped semiconductive material or conductive metal material. Individual of the conductive masses are atop and directly electrically coupled to individual of the lower channel-material strings. Upper channel-material strings of select-gate transistors are formed directly above the stack. Individual of the upper channel-material strings are directly above and directly electrically coupled to individual of the conductive masses. Other embodiments, including structure, are disclosed.

公开(公告)号：US11670379B2

公开(公告)日：2023-06-06

申请号：US17111751

申请日：2020-12-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshiaki Fukuzumi ,  Jun Fujiki ,  Shuji Tanaka ,  Masashi Yoshida ,  Masanobu Saito ,  Yoshihiko Kamata

IPC: G11C7/00 ,  G11C16/26 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  G11C16/04 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  G11C16/24 ,  G11C16/08 ,  H01L27/11565

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/24 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582

Abstract: Arrays of memory cells might include a data line, a source, a plurality of pass gates connected in series between the data line and the source, a plurality of unit column structures each having a respective plurality of series-connected non-volatile memory cells connected in series with a respective plurality of series-connected field-effect transistors, wherein a channel of each non-volatile memory cell of its respective plurality of series-connected non-volatile memory cells and a channel of each field-effect transistor of its respective plurality of series-connected field-effect transistors are selectively connected to one another, and a plurality of backside gate lines each connected to the second control gate of a respective pass gate of the plurality of pass gates, wherein, for each unit column structure of the plurality of unit column structures, the channel of a particular field-effect transistor of its respective plurality of field-effect transistors is capacitively coupled to the first channel of a respective pass gate of the plurality of pass gates.

公开(公告)号：US11657880B2

公开(公告)日：2023-05-23

申请号：US17861502

申请日：2022-07-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshiaki Fukuzumi ,  Jun Fujiki ,  Shuji Tanaka ,  Masashi Yoshida ,  Masanobu Saito ,  Yoshihiko Kamata

IPC: G11C7/00 ,  G11C16/26 ,  G11C16/04 ,  G11C16/10 ,  G11C11/56 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11556

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/10 ,  G11C11/5628 ,  G11C11/5671 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582

Abstract: Memory might include a plurality of series-connected non-volatile memory cells, a plurality of series-connected first field-effect transistors connected in series with the plurality of series-connected non-volatile memory cells, and a second field-effect transistor, wherein the channel of the second field-effect transistor is capacitively coupled to channels of the plurality of series-connected first field-effect transistors. The memory might further include a controller configured to cause the memory to selectively activate a selected non-volatile memory cell, activate each remaining non-volatile memory cell, increase a voltage level of the respective channel of each first field-effect transistor, selectively discharge the voltage level of the respective channel of each first field-effect transistor through the selected non-volatile memory cell, and determine whether the second field-effect transistor is activated in response to a remaining voltage level of the respective channel of each first field-effect transistor.

公开(公告)号：US20220181346A1

公开(公告)日：2022-06-09

申请号：US17557389

申请日：2021-12-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshiaki Fukuzumi ,  Jun Fujiki ,  Shuji Tanaka ,  Masashi Yoshida ,  Masanobu Saito ,  Yoshihiko Kamata

IPC: H01L27/11556 ,  G11C16/34 ,  G11C5/06 ,  G11C5/02 ,  H01L27/11582

Abstract: Arrays of memory cells might include a first upper data line, a second upper data line, a lower data line, a first pass gate selectively connected to the lower data line, a second pass gate connected to the first pass gate and selectively connected to the lower data line, a third pass gate selectively connected to the lower data line, a fourth pass gate connected to the third pass gate and selectively connected to the lower data line, unit column structures selectively connected to a respective one of the upper data lines and capacitively coupled to a first channel of a respective one of the pass gates, and control lines capacitively coupled to a second channel of a respective one of the pass gates.

公开(公告)号：US20220180938A1

公开(公告)日：2022-06-09

申请号：US17111751

申请日：2020-12-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshiaki Fukuzumi ,  Jun Fujiki ,  Shuji Tanaka ,  Masashi Yoshida ,  Masanobu Saito ,  Yoshihiko Kamata

IPC: G11C16/26 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  G11C16/24 ,  G11C16/08 ,  G11C16/04

Abstract: Arrays of memory cells might include a data line, a source, a plurality of pass gates connected in series between the data line and the source, a plurality of unit column structures each having a respective plurality of series-connected non-volatile memory cells connected in series with a respective plurality of series-connected field-effect transistors, wherein a channel of each non-volatile memory cell of its respective plurality of series-connected non-volatile memory cells and a channel of each field-effect transistor of its respective plurality of series-connected field-effect transistors are selectively connected to one another, and a plurality of backside gate lines each connected to the second control gate of a respective pass gate of the plurality of pass gates, wherein, for each unit column structure of the plurality of unit column structures, the channel of a particular field-effect transistor of its respective plurality of field-effect transistors is capacitively coupled to the first channel of a respective pass gate of the plurality of pass gates.

公开(公告)号：US20220180937A1

公开(公告)日：2022-06-09

申请号：US17111729

申请日：2020-12-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshiaki Fukuzumi ,  Jun Fujiki ,  Shuji Tanaka ,  Masashi Yoshida ,  Masanobu Saito ,  Yoshihiko Kamata

IPC: G11C16/26 ,  G11C16/04

Abstract: An array of memory cells might include a first data line, a second data line, a source, a capacitance selectively connected to the first data line, a string of series-connected non-volatile memory cells between the first data line and the capacitance, and a pass gate selectively connected between the second data line and the source, wherein an electrode of the capacitance is capacitively coupled to a channel of the pass gate.

公开(公告)号：US11386966B2

公开(公告)日：2022-07-12

申请号：US17111770

申请日：2020-12-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshiaki Fukuzumi ,  Jun Fujiki ,  Shuji Tanaka ,  Masashi Yoshida ,  Masanobu Saito ,  Yoshihiko Kamata

IPC: G11C11/34 ,  G11C16/26 ,  G11C16/04 ,  G11C16/10 ,  G11C11/56 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11556

Abstract: Memory might include a non-volatile memory cell, a capacitance selectively connected to the non-volatile memory cell, a field-effect transistor having a channel capacitively coupled to an electrode of the capacitance, and a controller for access of the non-volatile memory cell configured to cause the memory to increase a voltage level of the electrode of the capacitance, selectively discharge the voltage level of the electrode of the capacitance through the non-volatile memory cell responsive to a data state stored in the non-volatile memory cell, and determine whether the field-effect transistor is activated in response to a remaining voltage level of the electrode of the capacitance.

公开(公告)号：US11227869B1

公开(公告)日：2022-01-18

申请号：US17111746

申请日：2020-12-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshiaki Fukuzumi ,  Jun Fujiki ,  Shuji Tanaka ,  Masashi Yoshida ,  Masanobu Saito ,  Yoshihiko Kamata

IPC: H01L27/11556 ,  G11C5/06 ,  G11C5/02 ,  G11C16/34 ,  H01L27/11582

Abstract: Arrays of memory cells a plurality of sense lines each having a respective plurality of pass gates connected in series between a second data line and a source, and having a respective subset of unit column structures capacitively coupled to first channels of its respective plurality of pass gates, wherein, for each sense line of the plurality of sense lines, each unit column structure of its respective subset of unit column structures is connected to a respective first data line of a respective subset of first data lines.

公开(公告)号：US12080356B2

公开(公告)日：2024-09-03

申请号：US17876718

申请日：2022-07-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshiaki Fukuzumi ,  Jun Fujiki ,  Shuji Tanaka ,  Masashi Yoshida ,  Masanobu Saito ,  Yoshihiko Kamata

IPC: G11C16/04 ,  G11C16/26

CPC classification number: G11C16/26 ,  G11C16/0483

Abstract: Methods of forming integrated circuit structures for a capacitive sense NAND memory include forming a first semiconductor overlying a dielectric, forming a second semiconductor to be in contact with a first end of the first semiconductor, forming a third semiconductor to be in contact with a second end of the first semiconductor opposite the first end of the first semiconductor, forming a vertical channel material structure overlying the first semiconductor and having a channel material capacitively coupled to the first semiconductor, and forming a plurality of series-connected field-effect transistors adjacent the vertical channel material structure.