公开(公告)号：US20240347534A1

公开(公告)日：2024-10-17

申请号：US18749014

申请日：2024-06-20

申请人： Taiwan Semiconductor Manufacturing Company Ltd.

发明人： Shu-Uei Jang ,  Shih-Yao Lin ,  Chieh-Ning Feng ,  Shu-Yuan Ku

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L27/0886 ,  H01L21/823431 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7851

摘要： A method for making a semiconductor device includes: forming a first semiconductor fin structure and a second semiconductor fin structure over a substrate that both extend along a first lateral direction; forming a dummy gate structure that extends along a second lateral direction perpendicular to the first direction and straddles the first and second semiconductor fin structures; removing a portion of the dummy gate structure between the first and second semiconductor fin structures to form a trench, a width of the trench along the second direction decreasing with increasing depth toward the substrate; filling the trench with a dielectric material; and removing the second semiconductor fin structure and a portion of the dielectric material.

公开(公告)号：US20240332422A1

公开(公告)日：2024-10-03

申请号：US18732022

申请日：2024-06-03

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Yao Lin ,  Hsiao Wen Lee ,  Li-Jung Kuo ,  Chen-Ping Chen ,  Ming-Ching Chang

IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66

CPC分类号： H01L29/7851 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/66795

摘要： A semiconductor device in a first area includes first non-planar semiconductor structures separated with a first distance, and a first isolation region including a first layer and a second layer that collectively embed a lower portion of each of the first non-planar semiconductor structures. At least one of the first layer or second layer of the first isolation region is in a cured state. The semiconductor device in a second area includes second non-planar semiconductor structures separated with a second distance, and a second isolation region including a first layer and a second layer that collectively embed a lower portion of each of the second non-planar semiconductor structures. At least one of the first or second layer of the second isolation region is in a cured state.

公开(公告)号：US20240213344A1

公开(公告)日：2024-06-27

申请号：US18598781

申请日：2024-03-07

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Yao Lin ,  Chih-Han Lin ,  Hsiao Wen Lee

IPC分类号： H01L29/423 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/42392 ,  H01L29/0673 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/7831 ,  H01L29/78696 ,  H01L21/3065

摘要： A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. Each of the plurality of semiconductor layers extends along a first lateral direction. The semiconductor device includes a gate structure that extends along a second lateral direction and comprises at least a lower portion that wraps around each of the plurality of semiconductor layers. The lower portion of the gate structure comprises a plurality of first gate sections that are laterally aligned with the plurality of semiconductor layers, respectively, and wherein each of the plurality of first gate sections has ends that each extend along the second lateral direction and present a first curvature-based profile.

公开(公告)号：US20240176945A1

公开(公告)日：2024-05-30

申请号：US18437740

申请日：2024-02-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ching Hsu ,  Shih-Yao Lin ,  Yi-Lin Chuang

IPC分类号： G06F30/398 ,  G06F30/392 ,  G06N5/04 ,  G06N20/00

CPC分类号： G06F30/398 ,  G06F30/392 ,  G06N5/04 ,  G06N20/00

摘要： A method includes: training a machine learning model with a plurality of electronic circuit placement layouts; predicting, by the machine learning model, fix rates of design rule check (DRC) violations of a new electronic circuit placement layout; identifying hard-to-fix (HTF) DRC violations among the DRC violations based on the fix rates of the DRC violations of the new electronic circuit placement layout; and fixing, by an engineering change order (ECO) tool, the DRC violations.

公开(公告)号：US11967533B2

公开(公告)日：2024-04-23

申请号：US17355444

申请日：2021-06-23

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shu-Uei Jang ,  Shu-Yuan Ku ,  Shih-Yao Lin

IPC分类号： H01L29/78 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66

CPC分类号： H01L21/823481 ,  H01L21/31116 ,  H01L21/32137 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66545

摘要： A method includes forming a first semiconductor fin and a second semiconductor fin over a substrate that both extend along a first direction. The method includes forming a dielectric fin extending along the first direction and is disposed between the first and second semiconductor fins. The method includes forming a dummy gate structure extending along a second direction and straddling the first and second semiconductor fins and the dielectric fin. The method includes removing a portion of the dummy gate structure over the dielectric fin to form a trench by performing an etching process that includes a plurality of stages. Each of the plurality of stages includes a combination of anisotropic etching and isotropic etching such that a variation of a distance between respective inner sidewalls of the trench along the second direction is within a threshold.

公开(公告)号：US20240014293A1

公开(公告)日：2024-01-11

申请号：US17811739

申请日：2022-07-11

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuei-Yu Kao ,  Shih-Yao Lin ,  Chen-Ping Chen ,  Chih-Chung Chiu ,  Chih-Han Li ,  Ming-Ching Chang ,  Chao-Cheng Chen

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L29/775 ,  H01L29/786 ,  H01L29/423 ,  H01L29/40 ,  H01L21/762

CPC分类号： H01L29/66545 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696 ,  H01L29/42392 ,  H01L29/401 ,  H01L29/66553 ,  H01L29/6656 ,  H01L21/76224 ,  H01L27/088

摘要： Provided are devices with replacement structures and methods for fabricating such structures. A method includes forming a layer over a semiconductor material having a top surface in a horizontal plane; forming a dummy structure over the layer, wherein the dummy structure has sidewall, wherein the dummy structure lies directly over a first region of the layer and over a first region of the semiconductor material under the first region of the layer, and wherein the dummy structure does not lie directly over a second region of the layer or over a second region of the semiconductor material under the second region of the layer, and removing the second region of the layer and forming a side edge of the first region of the layer, wherein the side edge forms an angle of from 90 to 100 degrees with the horizontal plane.

公开(公告)号：US20240014073A1

公开(公告)日：2024-01-11

申请号：US18446943

申请日：2023-08-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Yao Lin ,  Chao-Cheng Chen ,  Chih-Han Lin ,  Chen-Ping Chen ,  Ming-Ching Chang ,  Chia-Hao Yu ,  Hsiao Wen Lee

IPC分类号： H01L21/8234 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L21/311 ,  H01L29/66 ,  H01L29/06 ,  H01L27/088

CPC分类号： H01L21/823431 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/78696 ,  H01L21/31144 ,  H01L29/66545 ,  H01L21/823418 ,  H01L29/66553 ,  H01L29/0665 ,  H01L27/0886

摘要： A method of fabricating a semiconductor device is described. A plurality of fins is formed over a substrate. Dummy gates are formed patterned over the fins, each dummy gate having a spacer on sidewalls of the patterned dummy gates. Recesses are formed in the fins using the patterned dummy gates as a mask. A passivation layer is formed over the fins and in the recesses in the fins. The passivation layer is patterned to leave a remaining passivation layer only in some of the recesses in the fins. Source and drain regions are epitaxially formed only in the recesses in the fins without the remaining passivation layer.

公开(公告)号：US11854899B2

公开(公告)日：2023-12-26

申请号：US17376960

申请日：2021-07-15

申请人： Taiwan Semiconductor Manufacturing Company Ltd.

发明人： Shih-Yao Lin ,  Chao-Cheng Chen ,  Chih-Han Lin ,  Chen-Ping Chen ,  Ming-Ching Chang ,  Chia-Hao Yu ,  Hsiao Wen Lee

IPC分类号： H01L21/8234 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L21/311 ,  H01L29/66 ,  H01L29/06 ,  H01L27/088

CPC分类号： H01L21/823431 ,  H01L21/31144 ,  H01L21/823418 ,  H01L27/0886 ,  H01L29/0665 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/78696

摘要： A method of fabricating a semiconductor device is described. A plurality of fins is formed over a substrate. Dummy gates are formed patterned over the fins, each dummy gate having a spacer on sidewalls of the patterned dummy gates. Recesses are formed in the fins using the patterned dummy gates as a mask. A passivation layer is formed over the fins and in the recesses in the fins. The passivation layer is patterned to leave a remaining passivation layer only in some of the recesses in the fins. Source and drain regions are epitaxially formed only in the recesses in the fins without the remaining passivation layer.

公开(公告)号：US20230369470A1

公开(公告)日：2023-11-16

申请号：US18359225

申请日：2023-07-26

申请人： Taiwan Semiconductor Manufacturing Company Ltd.

发明人： Shih-Yao Lin ,  Te-Yung Liu ,  Chih-Han Lin

IPC分类号： H01L29/66 ,  H01L29/78

CPC分类号： H01L29/6681 ,  H01L29/785

摘要： A semiconductor device and method for fabricating a semiconductor device includes etch selectivity tuning to enlarge epitaxy process windows. Through modification of etching processes and careful selection of materials, improvements in semiconductor device yield and performance can be delivered. Etch selectivity is controlled by using dilute gas, using assistive etch chemicals, controlling a magnitude of bias power used in the etching process, and controlling an amount of passivation gas used in the etching process, among other approaches. A recess is formed in a dummy fin in a region of the semiconductor where epitaxial growth occurs to further enlarge the epitaxy process window.

公开(公告)号：US20230163195A1

公开(公告)日：2023-05-25

申请号：US18158263

申请日：2023-01-23

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Yao Lin ,  Hsiao Wen Lee ,  Yu-Shan Cheng ,  Chao-Cheng Chen

IPC分类号： H01L29/66 ,  H01L29/423 ,  H01L21/764 ,  H01L29/786 ,  H01L29/06

CPC分类号： H01L29/6653 ,  H01L29/42392 ,  H01L21/764 ,  H01L29/78696 ,  H01L29/6656 ,  H01L29/0665

摘要： A semiconductor device includes a gate structure extending along a first lateral direction. The semiconductor device includes a source/drain structure disposed on one side of the gate structure along a second lateral direction, the second lateral direction perpendicular to the first lateral direction. The semiconductor device includes an air gap disposed between the gate structure and the source/drain structure along the second lateral direction, wherein the air gap is disposed over the source/drain structure.