公开(公告)号：US20240170336A1

公开(公告)日：2024-05-23

申请号：US18426852

申请日：2024-01-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuei-Yu Kao ,  Chao-Cheng Chen ,  Chih-Han Lin ,  Chen-Ping Chen ,  Ming-Ching Chang ,  Shih-Yao Lin ,  Chih-Chung Chiu

IPC分类号： H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L21/823468 ,  H01L21/823431 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66742 ,  H01L29/78618

摘要： A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. The semiconductor device includes a gate structure that comprises a lower portion and an upper portion, wherein the lower portion wraps around each of the plurality of semiconductor layers. The semiconductor device includes a gate spacer that extends along a sidewall of the upper portion of the gate structure and has a bottom surface. A portion of the bottom surface of the gate spacer and a top surface of a topmost one of the plurality of semiconductor layers form an angle that is less than 90 degrees.

公开(公告)号：US20240096705A1

公开(公告)日：2024-03-21

申请号：US18524242

申请日：2023-11-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuei-Yu Kao ,  Chen-Yui Yang ,  Hsien-Chung Huang ,  Chao-Cheng Chen ,  Shih-Yao Lin ,  Chih-Chung Chiu ,  Chih-Han Lin ,  Chen-Ping Chen ,  Ke-Chia Tseng ,  Ming-Ching Chang

IPC分类号： H01L21/8234 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L21/823468 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823462 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/78696

摘要： A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.

公开(公告)号：US20230343849A1

公开(公告)日：2023-10-26

申请号：US18344581

申请日：2023-06-29

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Ping Chen ,  Chih-Han Lin ,  Ming-Ching Chang ,  Chao-Cheng Chen

IPC分类号： H01L29/49 ,  H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L29/66 ,  H01L29/786 ,  H01L21/28 ,  H01L29/423

CPC分类号： H01L29/4983 ,  H01L29/7851 ,  H01L29/0847 ,  H01L29/0673 ,  H01L29/66795 ,  H01L29/78618 ,  H01L29/78696 ,  H01L21/28123 ,  H01L29/66545 ,  H01L29/42392

摘要： A semiconductor device is disclosed. The semiconductor device includes a substrate including a semiconductor material. The semiconductor device includes a conduction channel of a transistor disposed above the substrate. The conduction channel and the substrate include a similar semiconductor material. The semiconductor device includes a source/drain region extending from an end of the conduction channel. The semiconductor device includes a dielectric structure. The source/drain region is electrically coupled to the conduction channel and electrically isolated from the substrate by the dielectric structure.

公开(公告)号：US20230060742A1

公开(公告)日：2023-03-02

申请号：US17459865

申请日：2021-08-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Yao Lin ,  Chih-Han Lin ,  Chen-Ping Chen ,  Hsiao Wen Lee

IPC分类号： H01L21/8234 ,  H01L27/088

摘要： A semiconductor device includes a first stack structure, a second stack structure, and a third stack structure. Each of the stack structure includes semiconductor layers vertically spaced from one another. The first, second, and third stack structures all extend along a first lateral direction. The second stack structure is disposed between the first and third stack structures. The semiconductor device includes a first gate structure that extends along a second lateral direction and wraps around each of the semiconductor layers. The semiconductor layers of the first stack structure are coupled with respective source/drain structures. The semiconductor layers of the second stack structure are coupled with respective source/drain structures. The semiconductor layers of the third stack structure are coupled with a dielectric passivation layer.

公开(公告)号：US11552195B2

公开(公告)日：2023-01-10

申请号：US17230414

申请日：2021-04-14

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Yao Lin ,  Hsiao Wen Lee ,  Li-Jung Kuo ,  Chen-Ping Chen ,  Ming-Ching Chang

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/66

摘要： A semiconductor device in a first area includes first non-planar semiconductor structures separated with a first distance, and a first isolation region including a first layer and a second layer that collectively embed a lower portion of each of the first non-planar semiconductor structures. At least one of the first layer or second layer of the first isolation region is in a cured state. The semiconductor device in a second area includes second non-planar semiconductor structures separated with a second distance, and a second isolation region including a first layer and a second layer that collectively embed a lower portion of each of the second non-planar semiconductor structures. At least one of the first or second layer of the second isolation region is in a cured state.

公开(公告)号：US11923440B2

公开(公告)日：2024-03-05

申请号：US17873978

申请日：2022-07-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Yao Lin ,  Chen-Ping Chen ,  Kuei-Yu Kao ,  Hsiao Wen Lee ,  Chih-Han Lin

IPC分类号： H01L29/94 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/76 ,  H01L29/78

CPC分类号： H01L29/6681 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/785

摘要： A method of fabricating a semiconductor device is disclosed. The method includes forming semiconductor fins on a substrate. A first dummy gate is formed over the semiconductor fins. A recess is formed in the first dummy gate, and the recess is disposed between the semiconductor fins. A dummy fin material is formed in the recess. A portion of the dummy fin material is removed to expose an upper surface of the first dummy gate and to form a dummy fin. A second dummy gate is formed on the exposed upper surface of the first dummy gate.

公开(公告)号：US11908746B2

公开(公告)日：2024-02-20

申请号：US17460213

申请日：2021-08-28

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuei-Yu Kao ,  Chao-Cheng Chen ,  Chih-Han Lin ,  Chen-Ping Chen ,  Ming-Ching Chang ,  Shih-Yao Lin ,  Chih-Chung Chiu

IPC分类号： H01L21/8234 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L29/06

CPC分类号： H01L21/823468 ,  H01L21/823431 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/6656 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78618

摘要： A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. The semiconductor device includes a gate structure that comprises a lower portion and an upper portion, wherein the lower portion wraps around each of the plurality of semiconductor layers. The semiconductor device includes a gate spacer that extends along a sidewall of the upper portion of the gate structure and has a bottom surface. A portion of the bottom surface of the gate spacer and a top surface of a topmost one of the plurality of semiconductor layers form an angle that is less than 90 degrees.

公开(公告)号：US20230387272A1

公开(公告)日：2023-11-30

申请号：US18232544

申请日：2023-08-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Yao LIN ,  Chen-Ping Chen ,  Kuei-Yu Kao ,  Hsiao Wen Lee ,  Chih-Han Lin

IPC分类号： H01L29/66 ,  H01L27/088 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/06

CPC分类号： H01L29/6681 ,  H01L27/0886 ,  H01L29/785 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/66545 ,  H01L29/0649

摘要： A method of fabricating a semiconductor device is disclosed. The method includes forming semiconductor fins on a substrate. A first dummy gate is formed over the semiconductor fins. A recess is formed in the first dummy gate, and the recess is disposed between the semiconductor fins. A dummy fin material is formed in the recess. A portion of the dummy fin material is removed to expose an upper surface of the first dummy gate and to form a dummy fin. A second dummy gate is formed on the exposed upper surface of the first dummy gate.

公开(公告)号：US20230119370A1

公开(公告)日：2023-04-20

申请号：US18066777

申请日：2022-12-15

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Yao Lin ,  Hsiao Wen Lee ,  Li-Jung Kuo ,  Chen-Ping Chen ,  Ming-Ching Chang

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/66

摘要： A semiconductor device in a first area includes first non-planar semiconductor structures separated with a first distance, and a first isolation region including a first layer and a second layer that collectively embed a lower portion of each of the first non-planar semiconductor structures. At least one of the first layer or second layer of the first isolation region is in a cured state. The semiconductor device in a second area includes second non-planar semiconductor structures separated with a second distance, and a second isolation region including a first layer and a second layer that collectively embed a lower portion of each of the second non-planar semiconductor structures. At least one of the first or second layer of the second isolation region is in a cured state.

公开(公告)号：US20220367672A1

公开(公告)日：2022-11-17

申请号：US17873978

申请日：2022-07-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Yao LIN ,  Chen-Ping Chen ,  Kuei-Yu Kao ,  Hsiao Wen Lee ,  Chih-Han Lin

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78

摘要： A method of fabricating a semiconductor device is disclosed. The method includes forming semiconductor fins on a substrate. A first dummy gate is formed over the semiconductor fins. A recess is formed in the first dummy gate, and the recess is disposed between the semiconductor fins. A dummy fin material is formed in the recess. A portion of the dummy fin material is removed to expose an upper surface of the first dummy gate and to form a dummy fin. A second dummy gate is formed on the exposed upper surface of the first dummy gate.