公开(公告)号：US09082722B2

公开(公告)日：2015-07-14

申请号：US13849858

申请日：2013-03-25

Applicant: Raytheon Company

Inventor： Adrian D. Williams ,  Paul M. Alcorn

IPC: H01L21/311 ,  H01L29/66 ,  H01L29/812 ,  H01L21/8252 ,  H01L29/778 ,  H01L27/06 ,  H01L23/29 ,  H01L23/31 ,  H01L29/20

CPC classification number: H01L21/31144 ,  H01L21/8252 ,  H01L23/291 ,  H01L23/3171 ,  H01L27/0605 ,  H01L27/0629 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/66863 ,  H01L29/7786 ,  H01L29/812 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a semiconductor structure having a transistor device with a control electrode for controlling a flow of carriers between a first electrode and a second electrode. A passivation layer is deposited over the first electrode, the second electrode and the control electrode. An etch stop layer is deposited on the passivation layer over the control electrode. A dielectric layer is formed over the etch stop layer. A window is etched through a selected region in the dielectric layer over the control electrode, to expose a portion of the etch stop layer disposed over the control electrode. A metal layer is formed on a portion of the etch stop layer and the dielectric layer is also formed on the metal layer. A second metal layer is deposited on the portion of the dielectric layer formed on the first mentioned metal layer.

Abstract translation: 一种用于形成具有晶体管器件的半导体结构的方法，所述晶体管器件具有用于控制第一电极和第二电极之间的载流子流动的控制电极。 钝化层沉积在第一电极，第二电极和控制电极上。 蚀刻停止层沉积在控制电极上的钝化层上。 在蚀刻停止层上方形成介电层。 通过控制电极上的电介质层中的选定区域蚀刻窗口，以暴露设置在控制电极上的蚀刻停止层的一部分。 在蚀刻停止层的一部分上形成金属层，并且还在金属层上形成电介质层。 第二金属层沉积在形成在第一金属层上的电介质层的部分上。

公开(公告)号：US10720497B2

公开(公告)日：2020-07-21

申请号：US15791771

申请日：2017-10-24

Applicant: Raytheon Company

Inventor： Christopher J. MacDonald ,  Kenneth A. Wilson ,  Kamal Tabatabaie Alavi ,  Adrian D. Williams

IPC: H01L29/40 ,  H01L29/20 ,  H01L29/205 ,  H01L21/311 ,  H01L29/66 ,  H01L29/778 ,  H01L23/31

Abstract: A Field Effect Transistor (FET) having a source, drain, and gate disposed laterally along a surface of a semiconductor and a field plate structure: having one end connected to the source; and having a second end disposed between the gate and the drain and separated from the drain by a gap. A dielectric structure is disposed over the semiconductor, having: a first portion disposed under the second end of the field plate structure; and, a second, thinner portion under the gap.

公开(公告)号：US20180033744A1

公开(公告)日：2018-02-01

申请号：US15219327

申请日：2016-07-26

Applicant: Raytheon Company

Inventor： Fikret Altunkilic ,  Adrian D. Williams ,  Christopher J. MacDonald ,  Kamal Tabatabaie Alavi

IPC: H01L23/64 ,  H01L21/768 ,  H01L21/324 ,  H01L23/58

CPC classification number: H01L23/647 ,  H01L21/28575 ,  H01L21/324 ,  H01L21/67115 ,  H01L21/768 ,  H01L23/585 ,  H01L23/66 ,  H01L27/0605 ,  H01L29/812 ,  H01L2924/1423

Abstract: A method and structure, the structure having a substrate, an active device in an active device semiconductor region; of the substrate, a microwave transmission line, on the substrate, electrically connected to the active device, and microwave energy absorbing “dummy” fill elements on the substrate. The method includes providing a structure having a substrate, an active device region on a surface of the structure, an ohmic contact material on the active device region, and a plurality of “dummy” fill elements on the surface to provide uniform heating of the substrate during a rapid thermal anneal process, the ohmic contact material and the “dummy” fill elements having the same radiant energy reflectivity. The rapid thermal anneal processing forms an ohmic contact between an ohmic contact material and the active device region and simultaneously converts the “dummy” fill elements into microwave lossy “dummy” fill elements.

公开(公告)号：US09478652B1

公开(公告)日：2016-10-25

申请号：US14683812

申请日：2015-04-10

Applicant: Raytheon Company

Inventor： Adrian D. Williams

IPC: H01L21/02 ,  H01L29/778 ,  H01L29/66 ,  H01L29/47 ,  H01L21/768 ,  H01L21/311 ,  H01L23/31 ,  H01L29/205 ,  H01L23/66

CPC classification number: H01L29/7787 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0272 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76805 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76895 ,  H01L23/3171 ,  H01L23/3185 ,  H01L23/3192 ,  H01L23/485 ,  H01L23/66 ,  H01L27/0605 ,  H01L27/0629 ,  H01L28/60 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42316 ,  H01L29/475 ,  H01L29/66439 ,  H01L29/66462 ,  H01L29/7786 ,  H01L2223/6672 ,  H01L2223/6683

Abstract: A method for forming a semiconductor structure having a transistor device with a control electrode for controlling a flow of carriers between a first electrode and a second electrode. A passivation layer is deposited over the first electrode, the second electrode and the control electrode. An etch stop layer is deposited on the passivation layer over the control electrode. The etch stop layer includes the etch stop layer comprising: a first etch stop layer on the passivation layer, a buffer layer on the first etch stop layer, and a second etch stop layer on the buffer layer. A dielectric layer is formed over the etch stop layer. A window is etched through a selected region in the dielectric layer over the control electrode, to expose a portion of the etch stop layer disposed over the control electrode. A metal layer is formed on a portion of the etch stop layer and the dielectric layer is also formed on the metal layer. A second metal layer is deposited on the portion of the dielectric layer formed on the first mentioned metal layer.

Abstract translation: 一种用于形成具有晶体管器件的半导体结构的方法，所述晶体管器件具有用于控制第一电极和第二电极之间的载流子流动的控制电极。 钝化层沉积在第一电极，第二电极和控制电极上。 蚀刻停止层沉积在控制电极上的钝化层上。 蚀刻停止层包括蚀刻停止层，包括：钝化层上的第一蚀刻停止层，第一蚀刻停止层上的缓冲层，以及缓冲层上的第二蚀刻停止层。 在蚀刻停止层上方形成介电层。 通过控制电极上的电介质层中的选定区域蚀刻窗口，以暴露设置在控制电极上的蚀刻停止层的一部分。 在蚀刻停止层的一部分上形成金属层，并且还在金属层上形成电介质层。 第二金属层沉积在形成在第一金属层上的电介质层的部分上。

公开(公告)号：US20190123150A1

公开(公告)日：2019-04-25

申请号：US15791771

申请日：2017-10-24

Applicant: Raytheon Company

Inventor： Christopher J. MacDonald ,  Kenneth A. Wilson ,  Kamal Tabatabaie Alavi ,  Adrian D. Williams

IPC: H01L29/40 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L29/66 ,  H01L21/311

Abstract: A Field Effect Transistor (FET) having a source, drain, and gate disposed laterally along a surface of a semiconductor and a field plate structure: having one end connected to the source; and having a second end disposed between the gate and the drain and separated from the drain by a gap. A dielectric structure is disposed over the semiconductor, having: a first portion disposed under the second end of the field plate structure; and, a second, thinner portion under the gap.

公开(公告)号：US20140284661A1

公开(公告)日：2014-09-25

申请号：US13849858

申请日：2013-03-25

Applicant: RAYTHEON COMPANY

Inventor： Adrian D. Williams ,  Paul M. Alcorn

IPC: H01L21/311 ,  H01L29/812 ,  H01L29/66

CPC classification number: H01L21/31144 ,  H01L21/8252 ,  H01L23/291 ,  H01L23/3171 ,  H01L27/0605 ,  H01L27/0629 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/66863 ,  H01L29/7786 ,  H01L29/812 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a semiconductor structure having a transistor device with a control electrode for controlling a flow of carriers between a first electrode and a second electrode. A passivation layer is deposited over the first electrode, the second electrode and the control electrode. An etch stop layer is deposited on the passivation layer over the control electrode. A dielectric layer is formed over the etch stop layer. A window is etched through a selected region in the dielectric layer over the control electrode, to expose a portion of the etch stop layer disposed over the control electrode. A metal layer is formed on a portion of the etch stop layer and the dielectric layer is also formed on the metal layer. A second metal layer is deposited on the portion of the dielectric layer formed on the first mentioned metal layer.

Abstract translation: 一种用于形成具有晶体管器件的半导体结构的方法，所述晶体管器件具有用于控制第一电极和第二电极之间的载流子流动的控制电极。 钝化层沉积在第一电极，第二电极和控制电极上。 蚀刻停止层沉积在控制电极上的钝化层上。 在蚀刻停止层上方形成介电层。 通过控制电极上的电介质层中的选定区域蚀刻窗口，以暴露设置在控制电极上的蚀刻停止层的一部分。 在蚀刻停止层的一部分上形成金属层，并且还在金属层上形成介电层。 第二金属层沉积在形成在第一金属层上的电介质层的部分上。

公开(公告)号：US11038030B2

公开(公告)日：2021-06-15

申请号：US16846902

申请日：2020-04-13

Applicant: Raytheon Company

Inventor： Christopher J. MacDonald ,  Kenneth A. Wilson ,  Kamal Tabatabaie Alavi ,  Adrian D. Williams

IPC: H01L29/40 ,  H01L29/778 ,  H01L21/311 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66 ,  H01L23/31

Abstract: A Field Effect Transistor (FET) having a source, drain, and gate disposed laterally along a surface of a semiconductor and a field plate structure: having one end connected to the source; and having a second end disposed between the gate and the drain and separated from the drain by a gap. A dielectric structure is disposed over the semiconductor, having: a first portion disposed under the second end of the field plate structure; and, a second, thinner portion under the gap.

公开(公告)号：US20200243652A1

公开(公告)日：2020-07-30

申请号：US16846902

申请日：2020-04-13

Applicant: Raytheon Company

Inventor： Christopher J. MacDonald ,  Kenneth A. Wilson ,  Kamal Tabatabaie Alavi ,  Adrian D. Williams

IPC: H01L29/40 ,  H01L23/31 ,  H01L29/778 ,  H01L29/66 ,  H01L21/311 ,  H01L29/205 ,  H01L29/20

Abstract: A Field Effect Transistor (FET) having a source, drain, and gate disposed laterally along a surface of a semiconductor and a field plate structure: having one end connected to the source; and having a second end disposed between the gate and the drain and separated from the drain by a gap. A dielectric structure is disposed over the semiconductor, having: a first portion disposed under the second end of the field plate structure; and, a second, thinner portion under the gap.

公开(公告)号：US20190198346A1

公开(公告)日：2019-06-27

申请号：US16220248

申请日：2018-12-14

Applicant: Raytheon Company

Inventor： Kezia Cheng ,  Kamal Tabatabaie Alavi ,  Adrian D. Williams ,  Christopher J. MacDonald ,  Kiuchul Hwang

IPC: H01L21/321 ,  H01L21/285 ,  H01L21/3205 ,  H01L29/45

Abstract: A stack of layers providing an ohmic contact with the semiconductor, a lower metal layer of the stack is disposed in direct contact with the semiconductor; and a radiation absorption control layer disposed over the lower layer for controlling an amount of the radiant energy to be absorbed in the radiation absorption control layer during exposure of the stack to the radiation during a process used to alloy the stack with the semiconductor to form the ohmic contact.

公开(公告)号：US09887089B2

公开(公告)日：2018-02-06

申请号：US15285782

申请日：2016-10-05

Applicant: Raytheon Company

Inventor： Kiuchul Hwang ,  Dale M. Shaw ,  Adrian D. Williams

IPC: H01L21/28 ,  H01L21/033 ,  H01L21/768 ,  H01L51/00 ,  H01L21/285 ,  H01L29/423 ,  H01L21/283

CPC classification number: H01L21/28114 ,  H01L21/283 ,  H01L21/28587 ,  H01L29/42316

Abstract: A semiconductor structure having a T-shaped electrode. The electrode has a top portion and a narrower stem portion extending from the top portion to a surface of a substrate. A solid dielectric layer has side portions juxtaposed and abutting sidewalls of a lower portion of the stem of electrode. A bottom surface of the top portion is spaced from an upper surface portion by a non-solid dielectric, such as air.