公开(公告)号：US09646671B1

公开(公告)日：2017-05-09

申请号：US15288886

申请日：2016-10-07

Applicant: Kilopass Technology, Inc.

Inventor： Frank Guo ,  Jim Reaves

IPC: G11C11/34 ,  G11C11/39 ,  G11C13/00 ,  G11C11/36 ,  G11C11/00

CPC classification number: G11C11/39 ,  G11C11/00 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1675 ,  G11C11/1697 ,  G11C11/36 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/0069

Abstract: Techniques are provided for managing voltages applied to memory cells in a cross-point array during a write operation (e.g., to transition from a resistive state into a conductive state). The techniques apply to thyristor memory cells and non-thyristor memory cells. Bitlines, connected by a wordline, are preconditioned to a voltage level, by a precondition device, to write data to one or more memory cells at intersections of the bitlines and the wordline. Each bitline is coupled to a high impedance device, a detect device, a precondition device and a clamp device. When a memory cell on a first bitline transitions from a resistive state into a conductive state, it pulls a voltage level of the first-bit line level low. A first clamp device maintains the voltage level at a level to de-bias the first bitline from the wordline, while other memory cells to be written along the wordline remain biased.

公开(公告)号：US09318717B1

公开(公告)日：2016-04-19

申请号：US14588997

申请日：2015-01-05

Applicant: International Business Machines Corporation

Inventor： Ali Afzali-Ardakani ,  Tze-chiang Chen ,  Kailash Gopalakrishnan ,  Bahman Hekmatshoartabari ,  Young H. Kwark

IPC: G11C11/36 ,  H01L51/05 ,  H01L51/10 ,  G11C11/40 ,  G11C13/00 ,  H01L51/00

CPC classification number: H01L51/0587 ,  B82Y10/00 ,  G11C7/22 ,  G11C11/36 ,  G11C11/40 ,  G11C11/5664 ,  G11C13/0014 ,  G11C14/00 ,  G11C16/0466 ,  G11C2216/08 ,  H01L51/0055 ,  H01L51/0098 ,  H01L51/0508 ,  H01L51/0562 ,  H01L51/102 ,  Y10S977/774 ,  Y10S977/943

Abstract: An apparatus with a programmable response includes a semi-conductor device with a junction formed thereon, the junction having a built-in potential, a quantum well element proximate to the junction that provides an energy well within a depletion region of the junction. The energy well comprises one or more donor energy states that support electron trapping, and/or one or more acceptor energy states that support hole trapping; thereby modulating the built-in potential of the junction. The semi-conductor device may be a diode, a bipolar diode, a transistor, or the like. A corresponding method is also disclosed herein.

Abstract translation: 具有可编程响应的装置包括其上形成有结的半导体器件，该结具有内置电位，靠近该结的量子阱元件，其在该结的耗尽区内提供能量。 能量阱包括支持电子俘获的一个或多个施主能量状态和/或支持孔陷阱的一个或多个受主能量状态; 从而调节结的内置电位。 半导体器件可以是二极管，双极二极管，晶体管等。 本文还公开了相应的方法。

公开(公告)号：US09013913B2

公开(公告)日：2015-04-21

申请号：US14276229

申请日：2014-05-13

Applicant: Intermolecular, Inc.

Inventor： Yun Wang ,  Tony P. Chiang ,  Prashant B. Phatak

IPC: G11C13/00 ,  G11C11/00 ,  G11C7/00 ,  G11C17/06 ,  G11C5/02 ,  G11C5/06 ,  G11C13/02 ,  G11C11/36 ,  G11C13/04

CPC classification number: G11C13/02 ,  G11C7/00 ,  G11C11/36 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0021 ,  G11C13/0069 ,  G11C13/04 ,  G11C2013/0073 ,  G11C2013/0092 ,  G11C2213/72

Abstract: According to various embodiments, a resistive-switching memory element and memory element array that uses a bipolar switching includes a select element comprising only a single diode that is not a Zener diode. The resistive-switching memory elements described herein can switch even when a switching voltage less than the breakdown voltage of the diode is applied in the reverse-bias direction of the diode. The memory elements are able to switch during the very brief period when a transient pulse voltage is visible to the memory element, and therefore can use a single diode per memory cell.

Abstract translation: 根据各种实施例，使用双极开关的电阻式开关存储器元件和存储元件阵列包括仅包括不是齐纳二极管的单个二极管的选择元件。 即使当在二极管的反向偏置方向上施加小于二极管的击穿电压的开关电压时，本文所述的电阻式开关存储元件也可以切换。 存储器元件能够在瞬态脉冲电压对存储元件可见时的非常短的时间内进行切换，因此每个存储单元可以使用单个二极管。

公开(公告)号：US20150016185A1

公开(公告)日：2015-01-15

申请号：US14241379

申请日：2012-09-12

Applicant: Tsu-Jae King Liu ,  Wookhyun Kwon

Inventor： Tsu-Jae King Liu ,  Wookhyun Kwon

IPC: G11C11/38

CPC classification number: G11C11/38 ,  G11C11/36 ,  G11C11/50 ,  H01L27/1021

Abstract: A non-volatile electro-mechanical diode memory cell is described for implementation of compact (4F2) cross-point memory arrays. The electro-mechanical diode memory cells operate with relatively low set/reset voltages and excellent retention characteristics, and are multi-time programmable. Due to its simplicity, this electro-mechanical diode memory cell is attractive for implementation of three-dimensional memory arrays for higher storage density.

Abstract translation: 描述了用于实现紧凑（4F2）交叉点存储器阵列的非易失性机电二极管存储器单元。 机电二极管存储单元以相对低的设定/复位电压和优异的保持特性工作，并且是多时间可编程的。 由于其简单性，该机电二极管存储单元对于实现用于更高存储密度的三维存储器阵列是有吸引力的。

公开(公告)号：US20120300544A1

公开(公告)日：2012-11-29

申请号：US13571094

申请日：2012-08-09

Applicant: Wing K. Luk ,  Robert H. Dennard

Inventor： Wing K. Luk ,  Robert H. Dennard

IPC: G11C11/36

CPC classification number: G11C11/36 ,  G11C11/404

Abstract: A gated diode memory cell is provided, including one or more transistors, such as field effect transistors (“FETs”), and a gated diode in signal communication with the FETs such that the gate of the gated diode is in signal communication with the source of a first FET, wherein the gate of the gated diode forms one terminal of the storage cell and the source of the gated diode forms another terminal of the storage cell, the drain of the first FET being in signal communication with a bitline (“BL”) and the gate of the first FET being in signal communication with a write wordline (“WLw”), and the source of the gated diode being in signal communication with a read wordline (“WLr”).

Abstract translation: 提供了门控二极管存储单元，其包括一个或多个晶体管，例如场效应晶体管（FET）以及与FET进行信号通信的门控二极管，使得门控二极管的栅极与源极 第一FET，其中栅极二极管的栅极形成存储单元的一个端子，栅极二极管的源极形成存储单元的另一个端子，第一FET的漏极与位线（BL）信号通信，并且 第一FET的栅极与写入字线（WLw）进行信号通信，门控二极管的源极与读取字线（WLr）进行信号通信。

公开(公告)号：US08072791B2

公开(公告)日：2011-12-06

申请号：US11819041

申请日：2007-06-25

Applicant: S. Brad Herner ,  Mark H. Clark ,  Tanmay Kumar

Inventor： S. Brad Herner ,  Mark H. Clark ,  Tanmay Kumar

IPC: G11C11/00 ,  G11C11/36

CPC classification number: G11C11/36 ,  H01L27/101 ,  H01L27/1021

Abstract: A method of making a nonvolatile memory device includes forming a first electrode, forming at least one nonvolatile memory cell comprising a silicon, germanium or silicon-germanium diode, doping the diode with at least one of nitrogen or carbon, and forming a second electrode over the at least one nonvolatile memory cell.

Abstract translation: 制造非易失性存储器件的方法包括：形成第一电极，形成至少一个包括硅，锗或硅 - 锗二极管的非易失性存储单元，用氮或碳中的至少一种掺杂二极管，并形成第二电极 所述至少一个非易失性存储单元。

公开(公告)号：US07911823B2

公开(公告)日：2011-03-22

申请号：US12123827

申请日：2008-05-20

Applicant: Takuya Futatsuyama ,  Koji Hosono ,  Toshiaki Edahiro ,  Naoya Tokiwa ,  Kazushige Kanda ,  Shigeo Ohshima

Inventor： Takuya Futatsuyama ,  Koji Hosono ,  Toshiaki Edahiro ,  Naoya Tokiwa ,  Kazushige Kanda ,  Shigeo Ohshima

IPC: G11C11/00 ,  G11C7/00 ,  G11C7/02 ,  G11C7/12 ,  G11C8/08

CPC classification number: G11C11/36

Abstract: A method of programming a non-volatile memory device with memory cells formed of variable resistance elements and disposed between word lines and bit lines, includes: previously charging a selected word line and a selected bit line together with a non-selected word line and a non-selected bit line up to a certain voltage; and further charging the selected word line and the non-selected bit line up to a program voltage higher than the certain voltage and a program-block voltage, respectively, and simultaneously discharging the selected bit line.

Abstract translation: 一种使用由可变电阻元件形成并且设置在字线和位线之间的存储单元来编程非易失性存储器件的方法包括：预先对所选择的字线和所选择的位线以及未选择的字线和 非选择位线达到一定电压; 并且进一步对所选字线和未选择的位线进行充电，直到分别高于特定电压和编程块电压的编程电压，并同时对所选择的位线进行放电。

公开(公告)号：US20090080254A1

公开(公告)日：2009-03-26

申请号：US12326706

申请日：2008-12-02

Applicant: Yi Ying Liao ,  Wen Jer Tsai ,  Chih Chieh Yeh

Inventor： Yi Ying Liao ,  Wen Jer Tsai ,  Chih Chieh Yeh

IPC: G11C16/02 ,  G11C11/36

CPC classification number: G11C11/36 ,  B82Y10/00 ,  G11C16/02 ,  G11C2216/06 ,  H01L27/1021 ,  H01L29/8616

Abstract: A memory integrated circuit has memory arrays that are vertically layered. These memory arrays include word lines and bit lines. Intersections between the word lines and the bit lines include a diode and a memory state storage element. The diode and the memory storage element are connected in between a word line and a bit line. The diode at the intersections includes a first diode node and a second diode node. Various aspects of the memory integrated circuit are electrically interconnected in various ways, such as corresponding word lines, corresponding first diode nodes, or corresponding second diode nodes of different memory arrays being electrically interconnected. Various aspects of the memory integrated circuit are isolated in various ways, such as word lines, first diode nodes, or second diode nodes of different memory arrays being isolated.

Abstract translation: 存储器集成电路具有垂直分层的存储器阵列。 这些存储器阵列包括字线和位线。 字线和位线之间的交点包括二极管和存储器状态存储元件。 二极管和存储器存储元件连接在字线和位线之间。 交叉处的二极管包括第一二极管节点和第二二极管节点。 存储器集成电路的各个方面以各种方式电互连，例如相应的字线，对应的第一二极管节点或不同存储器阵列的相应的第二二极管节点电互连。 存储器集成电路的各个方面以各种方式隔离，例如隔离不同存储器阵列的字线，第一二极管节点或第二二极管节点。

公开(公告)号：US20070285971A1

公开(公告)日：2007-12-13

申请号：US11761808

申请日：2007-06-12

Applicant: HARUKI TODA ,  KOICHI KUBO

Inventor： HARUKI TODA ,  KOICHI KUBO

IPC: G11C11/36

CPC classification number: G11C8/08 ,  G11C11/36 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0042 ,  G11C2013/009 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1266 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1675

Abstract: A resistance change memory device including: a substrate; cell arrays stacked thereabove, each including a matrix layout of memory cells; a write circuit configured to write a pair cell constituted by two neighboring memory cells; and a read circuit configured to read complementary resistance value states of the pair cell as one bit of data, wherein the memory cell includes a variable resistance element for storing as information a resistance value. The variable resistance element has: a recording layer formed of a composite compound containing at least one transition element and a cavity site for housing a cation ion; and electrodes formed on the opposite sides of the recording layer, one of the electrodes serving as a cation source in a write or erase mode for supplying a cation to the recording layer to be housed in the cavity site therein.

Abstract translation: 一种电阻变化存储器件，包括：衬底; 单元阵列堆叠在其上，每个包括存储单元的矩阵布局; 写入电路，被配置为写入由两个相邻存储器单元构成的对单元; 以及读取电路，被配置为读取所述对单元的互补电阻值状态作为数据的一位，其中所述存储单元包括用于存储作为信息电阻值的可变电阻元件。 可变电阻元件具有：由包含至少一个过渡元素和用于容纳阳离子离子的空腔部位的复合化合物形成的记录层; 以及形成在记录层的相对侧上的电极，其中一个电极用作写入或擦除模式中的阳离子源，用于将阳离子供应到要容纳在其中的空腔位置的记录层。

公开(公告)号：US20070285969A1

公开(公告)日：2007-12-13

申请号：US11761738

申请日：2007-06-12

Applicant: Haruki Toda ,  Koichi Kubo

Inventor： Haruki Toda ,  Koichi Kubo

IPC: G11C11/36

CPC classification number: G11C8/08 ,  G11C11/36 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0042 ,  G11C2013/009 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/126 ,  H01L45/147 ,  H01L45/1675

Abstract: A resistance change memory device including: a substrate; cell arrays stacked thereabove, each including a matrix layout of memory cells; a write circuit configured to write a pair cell constituted by two neighboring memory cells; and a read circuit configured to read complementary resistance value states of the pair cell as one bit of data, wherein the memory cell includes a variable resistance element for storing as information a resistance value, and wherein the variable resistance element has a recording layer formed of a first composite compound expressed by AxMyOz (where “A” and “M” are cation elements different from each other; “O” oxygen; and 0.5≦x≦1.5, 0.5≦y≦2.5 and 1.5≦z≦4.5) and a second composite compound containing at least one transition element and a cavity site for housing a cation ion.

Abstract translation: 一种电阻变化存储器件，包括：衬底; 单元阵列堆叠在其上，每个包括存储单元的矩阵布局; 写入电路，被配置为写入由两个相邻存储器单元构成的对单元; 以及读取电路，被配置为读取所述对单元的互补电阻值状态作为数据的一位，其中所述存储单元包括用于存储作为信息的电阻值的可变电阻元件，并且其中所述可变电阻元件具有由 由A M和Y M表示的第一复合化合物（其中“A”和“M”是彼此不同的阳离子元素; “O”氧;和0.5 <= x <= 1.5,0.5 <= y <= 2.5和1.5 <= z <= 4.5）和第二复合化合物，其含有至少一个过渡元素和用于容纳阳离子离子的空腔部位 。