知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

364 records (took 0.023 seconds)

    Dynamic random access memory (DRAM) cell, DRAM device and storage method
    1.
    发明授权
    Dynamic random access memory (DRAM) cell, DRAM device and storage method 有权

    公开(公告)号：US10957375B2

    公开(公告)日：2021-03-23

    申请号：US16883635

    申请日：2020-05-26

    Applicant: Changxin Memory Technologies, Inc.

    Inventor： Kei Kang Hung ,  Qi-An Xu

    IPC: G11C11/36 ,  G11C11/408 ,  G11C11/4091

    Abstract: A DRAM cell includes a transistor, a first diode and a second diode. The transistor has a gate electrically coupled to a word line of an address decoder and a drain electrically coupled to a bit line of the address decoder. The bit line is coupled to a power supply voltage. An anode and a cathode of the first diode are coupled to a cathode and an anode of the second diode, respectively. Each of the first diode and the second diode is coupled at a first end to a source of the transistor at a first node, and at a second end to a node voltage at the second node. A DRAM device includes an address decoder and DRAM cells. A storage method for a DRAM device includes writing data into the DRAM cells and reading data from the DRAM cells.

    Process of manufacturing an avalanche diode
    3.
    发明授权
    Process of manufacturing an avalanche diode 有权

    公开(公告)号：US10290760B2

    公开(公告)日：2019-05-14

    申请号：US16017492

    申请日：2018-06-25

    Applicant: SensL Technologies Ltd.

    Inventor： Kevin Michael O'Neill ,  John Carlton Jackson ,  Liam Wall

    IPC: G11C11/36 ,  G11C11/34 ,  H01L31/107 ,  H01L31/0224 ,  H01L27/144 ,  H01L31/18 ,  H01L31/02

    Abstract: In one form, a process of manufacturing an avalanche photodiode includes forming an insulating layer over an active region of a semiconductor substrate. A shallow terminal of the avalanche photodiode is defined using a first patterned mask. A first dopant is implanted through the first patterned mask and the insulating layer to form the shallow terminal. The first patterned mask is removed. A deep terminal of the avalanche photodiode is defined using second patterned mask. A second dopant is implanted through the second patterned mask and insulating layer to form the deep terminal of the avalanche photodiode. A respective terminal of at least one of the shallow terminal and the deep terminal is defined using a respective patterned mask that forms at least two regions that are spatially separated from each other with no implanted structure located in a space therebetween.

    Semiconductor integrated circuit
    6.
    发明授权
    Semiconductor integrated circuit 有权
    半导体集成电路

    公开(公告)号：US09431065B2

    公开(公告)日：2016-08-30

    申请号：US14656697

    申请日：2015-03-12

    Applicant: FUJI ELECTRIC CO., LTD.

    Inventor： Mutsuo Nishikawa ,  Kazuhiro Matsunami ,  Yuko Fujimoto

    IPC: G11C11/36 ,  G11C5/06 ,  G11C7/00 ,  G11C7/24 ,  G11C16/06 ,  G11C16/10 ,  G11C16/12 ,  G11C16/22 ,  G11C16/30

    CPC classification number: G11C5/06 ,  G11C7/00 ,  G11C7/24 ,  G11C16/06 ,  G11C16/10 ,  G11C16/12 ,  G11C16/22 ,  G11C16/30 ,  H01L27/0255

    Abstract: A semiconductor integrated circuit that exhibits an enhanced surge withstand voltage of a nonvolatile memory and has a reduced chip area, having a nonvolatile memory and a Zener diode connected in parallel between a write terminal and a ground terminal. The nonvolatile memory is connected to the write terminal by a write terminal line and to a common connection point by a first ground line. The cathode of the Zener diode is connected to the write terminal line. The anode of the Zener diode is connected to the specified connection point by a second ground line. The first ground line and the second ground line are connected to the specified connection point.

    Abstract translation: 一种半导体集成电路，其具有非易失性存储器的增强的耐冲击耐受电压并且具有减小的芯片面积，其具有在写入端子和接地端子之间并联连接的非易失性存储器和齐纳二极管。 非易失性存储器通过写入端子线连接到写入端子，并通过第一接地线连接到公共连接点。 齐纳二极管的阴极连接到写入端子线。 齐纳二极管的阳极通过第二个接地线连接到指定的连接点。 第一个接地线和第二个接地线连接到指定的连接点。

    Memory diodes
    7.
    发明授权
    Memory diodes 有权
    存储二极管

    公开(公告)号：US09172034B2

    公开(公告)日：2015-10-27

    申请号：US13818100

    申请日：2011-09-18

    Applicant: Avner Rothschild

    Inventor： Avner Rothschild

    IPC: H01L45/00 ,  G11C11/36 ,  G11C13/00

    CPC classification number: H01L45/085 ,  G11C11/36 ,  G11C13/00 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  H01L45/1253

    Abstract: A memory cell (32C), including a first non-insulator (34C) and a second non-insulator (40C), different from the first non-insulator. The second non-insulator forms a junction (46C) with the first non-insulator. The cell further includes a first electrode (48C) which is connected to the first non-insulator and a second electrode (50C) which is connected to the second non-insulator. At least one of the first and second non-insulators is chosen from a group consisting of a solid electrolyte and a mixed ionic electronic conductor and has an ionic transference number less than 1 and greater than or equal to 0.5.

    Abstract translation: 一种与第一非绝缘体不同的包括第一非绝缘体（34C）和第二非绝缘体（40C）的存储单元（32C）。 第二非绝缘体与第一非绝缘体形成结（46C）。 电池还包括连接到第一非绝缘体的第一电极（48C）和连接到第二非绝缘体的第二电极（50C）。 第一和第二非绝缘体中的至少一个选自由固体电解质和混合离子电子导体组成的组，并且具有小于1且大于或等于0.5的离子转移数。

    Bipolar resistive-switching memory with a single diode per memory cell
    8.
    发明授权
    Bipolar resistive-switching memory with a single diode per memory cell 有权
    每个存储单元具有单个二极管的双极电阻开关存储器

    公开(公告)号：US08750021B2

    公开(公告)日：2014-06-10

    申请号：US13957324

    申请日：2013-08-01

    Applicant: Intermolecular, Inc.

    Inventor： Yun Wang ,  Tony P. Chiang ,  Prashant B. Phatak

    IPC: G11C11/36 ,  G11C7/00 ,  G11C17/06 ,  G11C5/02 ,  G11C13/00 ,  G11C13/02 ,  G11C13/04

    CPC classification number: G11C13/02 ,  G11C7/00 ,  G11C11/36 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0021 ,  G11C13/0069 ,  G11C13/04 ,  G11C2013/0073 ,  G11C2013/0092 ,  G11C2213/72

    Abstract: According to various embodiments, a resistive-switching memory element and memory element array that uses a bipolar switching includes a select element comprising only a single diode that is not a Zener diode. The resistive-switching memory elements described herein can switch even when a switching voltage less than the breakdown voltage of the diode is applied in the reverse-bias direction of the diode. The memory elements are able to switch during the very brief period when a transient pulse voltage is visible to the memory element, and therefore can use a single diode per memory cell.

    Abstract translation: 根据各种实施例，使用双极开关的电阻式开关存储器元件和存储元件阵列包括仅包括不是齐纳二极管的单个二极管的选择元件。 即使当在二极管的反向偏置方向上施加小于二极管的击穿电压的开关电压时，这里描述的电阻式开关存储元件也可以切换。 存储器元件能够在瞬态脉冲电压对存储元件可见时的非常短的时间内进行切换，因此每个存储器单元可以使用单个二极管。

    Single device driver circuit to control three-dimensional memory element array
    9.
    发明授权
    Single device driver circuit to control three-dimensional memory element array 有权
    单器件驱动电路控制三维存储元件阵列

    公开(公告)号：US08659932B2

    公开(公告)日：2014-02-25

    申请号：US13608098

    申请日：2012-09-10

    Applicant: Roy E. Scheuerlein

    Inventor： Roy E. Scheuerlein

    IPC: G11C11/00 ,  G11C11/36

    CPC classification number: G11C13/0026 ,  B82Y10/00 ,  G11C7/12 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/025 ,  G11C17/165 ,  G11C2013/0073 ,  G11C2213/35 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/0688

    Abstract: A memory device includes diode plus resistivity switching element memory cells coupled between bit and word lines, single device bit line drivers with gates coupled to a bit line decoder control lead, sources/drains coupled to a bit line driver, and drains/sources coupled to bit lines, single device word line drivers with gates coupled to a word line decoder control lead, sources/drains coupled to a word line driver output, and drains/sources coupled to word lines, a first bleeder diode coupled between a bit line and a first bleeder diode controller, and a second bleeder diode coupled between a word line and a second bleeder diode controller. The first bleeder diode controller connects the first bleeder diode to low voltage in response to a bit line decoder signal. The second bleeder diode controller connects the second bleeder diode to high voltage in response to a word line decoder signal.

    Abstract translation: 存储器件包括耦合在位和字线之间的二极管加电阻率开关元件存储单元，单个器件位线驱动器，其栅极耦合到位线解码器控制引线，耦合到位线驱动器的源极/漏极以及耦合到 位线，具有耦合到字线解码器控制引线的栅极的单器件字线驱动器，耦合到字线驱动器输出的源极/漏极以及耦合到字线的漏极/源极，耦合在位线和 第一泄放二极管控制器和耦合在字线和第二泄放二极管控制器之间的第二泄放二极管。 第一泄放二极管控制器响应于位线解码器信号将第一泄放二极管连接到低电压。 第二泄放二极管控制器响应于字线解码器信号将第二泄放二极管连接到高电压。

    Random access memory circuit
    10.
    发明授权
    Random access memory circuit 有权
    随机存取存储器电路

    公开(公告)号：US08456885B2

    公开(公告)日：2013-06-04

    申请号：US12535261

    申请日：2009-08-04

    Applicant: Derek Tolmie ,  Arnaud Laflaquiere ,  Francois Roy

    Inventor： Derek Tolmie ,  Arnaud Laflaquiere ,  Francois Roy

    IPC: G11C11/36

    CPC classification number: G11C13/04 ,  H01L27/14609 ,  H04N5/335 ,  H04N5/37452 ,  H04N5/37457

    Abstract: A random access memory circuit includes a plurality of pixels, each having a light sensitive area and a light blocking layer arranged over at least each of the light sensitive areas. In an alternative embodiment, the circuit includes a plurality of memory elements for storing data. Each memory element may comprise a bit node formed between a photodiode, having a light arranged over the photodiode, and a switching element, where data may be stored. The circuit may also include a plurality of reading and writing circuits for reading and writing data to and from the memory cells.

    Abstract translation: 随机存取存储器电路包括多个像素，每个像素具有光敏区域和在至少每个光敏区域上布置的遮光层。 在替代实施例中，电路包括用于存储数据的多个存储元件。 每个存储元件可以包括形成在具有布置在光电二极管上的光的光电二极管之间的位节点和可以存储数据的开关元件。 电路还可以包括用于从存储器单元读取和写入数据的多个读取和写入电路。

Patent Agency Ranking