公开(公告)号：US11977940B2

公开(公告)日：2024-05-07

申请号：US17369449

申请日：2021-07-07

Applicant: Kioxia Corporation

Inventor： Akihisa Fujimoto ,  Toshitada Saito ,  Noriya Sakamoto ,  Atsushi Kondo

IPC: G11C5/02 ,  G06K19/077 ,  G11C5/06 ,  G11C11/4074 ,  G11C16/02 ,  G11C16/30

CPC classification number: G06K19/07732 ,  G06K19/07733 ,  G06K19/07743 ,  G11C5/06 ,  G11C11/4074 ,  G11C16/02 ,  G11C16/30

Abstract: According to one embodiment, there is provided a memory card including a first surface, a second surface, and 1st to Nth terminal groups. The first surface includes first to Nth rows, where N is an integer of two or greater. The second surface faces the opposite side from the first surface. The 1st to Nth terminal groups are placed in the first to Nth rows. The 1st terminal group includes terminals to which differential clock signals are assigned, terminals to which single-ended signals are assigned, and a terminal to which a first power supply voltage is assigned. Kth terminal group, where K is an integer no smaller than two and no greater than N, includes terminals to which differential data signals are assigned.

公开(公告)号：US11677021B2

公开(公告)日：2023-06-13

申请号：US18092727

申请日：2023-01-03

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach

IPC: H01L29/78 ,  G11C16/02 ,  G11C11/404 ,  G11C11/4097 ,  H10B10/00 ,  H10B12/00 ,  H10B43/20 ,  H10B69/00 ,  H10B63/00 ,  G11C11/412 ,  G11C16/04

CPC classification number: H01L29/78 ,  G11C11/404 ,  G11C11/4097 ,  G11C16/02 ,  H01L29/7841 ,  H10B10/12 ,  H10B12/20 ,  H10B43/20 ,  H10B63/30 ,  H10B69/00 ,  G11C11/412 ,  G11C16/0483 ,  G11C2213/71

Abstract: A semiconductor device, the device comprising: a first silicon layer comprising first single crystal silicon; an isolation layer disposed over said first silicon layer; a first metal layer disposed over said isolation layer; a second metal layer disposed over said first metal layer; a first level comprising a plurality of transistors, said first level disposed over said second metal layer, wherein said isolation layer comprises an oxide to oxide bond surface, wherein said plurality of transistors comprise a second single crystal silicon region; and a plurality of capacitors, wherein said plurality of capacitors comprise functioning as a decoupling capacitor to mitigate power supply noise.

公开(公告)号：US09449706B2

公开(公告)日：2016-09-20

申请号：US14257188

申请日：2014-04-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Jun Koyama

IPC: G11C16/34 ,  G11C16/02 ,  G11C16/04 ,  H01L27/115 ,  H01L27/12 ,  G11C11/403 ,  G11C8/08

CPC classification number: G11C14/0018 ,  G11C8/08 ,  G11C11/401 ,  G11C11/403 ,  G11C16/02 ,  G11C16/0408 ,  G11C16/0433 ,  G11C16/34 ,  H01L27/1156 ,  H01L27/1225

Abstract: A memory device in which data can be retained for a long time is provided. The memory device includes a memory element and a transistor which functions as a switching element for controlling supply, storage, and release of electrical charge in the memory element. The transistor includes a second gate electrode for controlling the threshold voltage in addition to a normal gate electrode. Further, the off-state current of the transistor is extremely low because an active layer thereof includes an oxide semiconductor. In the memory device, data is stored not by injection of electrical charge to a floating gate surrounded by an insulating film at high voltage but by control of the amount of electrical charge of the memory element through the transistor whose off-state current is extremely low.

Abstract translation: 提供了能够长时间保持数据的存储装置。 存储器件包括存储元件和用作控制存储元件中电荷的供应，存储和释放的开关元件的晶体管。 晶体管包括用于除正常栅电极之外控制阈值电压的第二栅电极。 此外，晶体管的截止电流极低，因为其有源层包括氧化物半导体。 在存储装置中，数据不是通过将电荷注入到由绝缘膜高压包围的浮动栅极而是通过截止状态电流非常低的晶体管控制存储元件的电荷量来存储的 。

公开(公告)号：US09302089B2

公开(公告)日：2016-04-05

申请号：US14259397

申请日：2014-04-23

Applicant: ORIDION MEDICAL 1987 LTD.

Inventor： David P. Besko

IPC: A61F5/44 ,  A61M39/10 ,  G11C16/02 ,  H01R9/11 ,  H01R13/66

CPC classification number: A61M39/10 ,  A61M39/1011 ,  A61M2039/1005 ,  A61M2039/1022 ,  A61M2039/1044 ,  A61M2205/43 ,  A61M2205/52 ,  A61M2205/6018 ,  A61M2205/6027 ,  G11C16/02 ,  H01R9/11 ,  H01R13/6616

Abstract: Tube connector including two conductive elements and a resistor and/or capacitor electrically connected therebetween, the two elements arranged such that an electrical circuit including the two conductive elements and the resistor and/or capacitor will be closed when the tube connector mates with a device connector of a medical device.

Abstract translation: 管连接器包括两个导电元件和电连接在它们之间的电阻器和/或电容器，两个元件布置成使得当管连接器与器件连接器配合时，包括两个导电元件和电阻器和/或电容器的电路将被闭合 的医疗器械。

公开(公告)号：US20160079245A1

公开(公告)日：2016-03-17

申请号：US14950624

申请日：2015-11-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Keitaro IMAI ,  Jun KOYAMA

IPC: H01L27/108 ,  H01L29/786

CPC classification number: H01L27/10802 ,  G11C11/404 ,  G11C11/405 ,  G11C16/02 ,  H01L21/8258 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/0922 ,  H01L27/105 ,  H01L27/1156 ,  H01L27/12 ,  H01L27/1225 ,  H01L29/7869

Abstract: The semiconductor device includes: a transistor having an oxide semiconductor layer; and a logic circuit formed using a semiconductor material other than an oxide semiconductor. One of a source electrode and a drain electrode of the transistor is electrically connected to at least one input of the logic circuit, and at least one input signal is applied to the logic circuit through the transistor. The off-current of the transistor is preferably 1×10−13 A or less.

Abstract translation: 半导体器件包括：具有氧化物半导体层的晶体管; 以及使用除了氧化物半导体之外的半导体材料形成的逻辑电路。 晶体管的源电极和漏电极中的一个电连接到逻辑电路的至少一个输入端，并且至少一个输入信号通过晶体管施加到逻辑电路。 晶体管的截止电流优选为1×10-13A以下。

公开(公告)号：US09214233B2

公开(公告)日：2015-12-15

申请号：US13895591

申请日：2013-05-16

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Chung-Zen Chen ,  Yang-Chieh Lin ,  Chung-Shan Kuo

IPC: G11C16/16 ,  G11C16/02 ,  G11C16/08

CPC classification number: G11C16/14 ,  G11C16/02 ,  G11C16/0408 ,  G11C16/08 ,  G11C16/16

Abstract: A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.

Abstract translation: 一种非易失性存储器件，包括存储器阵列，该存储器阵列具有被组织为扇区的多个存储器单元，每个扇区具有与多个本地字线相关联的主字线，每个本地字线通过 各自的本地字线驱动电路，每个本地字线驱动电路由耦合在相应主字线和相应本地字线之间的第一MOS晶体管和耦合在相应本地字线和第一 偏置端子

公开(公告)号：US09202546B2

公开(公告)日：2015-12-01

申请号：US12910908

申请日：2010-10-25

Applicant: Shunpei Yamazaki ,  Keitaro Imai ,  Jun Koyama

Inventor： Shunpei Yamazaki ,  Keitaro Imai ,  Jun Koyama

IPC: H01L29/10 ,  G11C11/404 ,  G11C11/405 ,  G11C16/02 ,  H01L21/8258 ,  H01L27/06 ,  H01L27/088 ,  H01L27/105 ,  H01L27/115 ,  H01L27/12 ,  H01L27/092

CPC classification number: H01L27/10802 ,  G11C11/404 ,  G11C11/405 ,  G11C16/02 ,  H01L21/8258 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/0922 ,  H01L27/105 ,  H01L27/1156 ,  H01L27/12 ,  H01L27/1225 ,  H01L29/7869

Abstract: The semiconductor device includes: a transistor having an oxide semiconductor layer; and a logic circuit formed using a semiconductor material other than an oxide semiconductor. One of a source electrode and a drain electrode of the transistor is electrically connected to at least one input of the logic circuit, and at least one input signal is applied to the logic circuit through the transistor. The off-current of the transistor is preferably 1×10−13 A or less.

Abstract translation: 半导体器件包括：具有氧化物半导体层的晶体管; 以及使用除了氧化物半导体之外的半导体材料形成的逻辑电路。 晶体管的源电极和漏电极中的一个电连接到逻辑电路的至少一个输入端，并且至少一个输入信号通过晶体管施加到逻辑电路。 晶体管的截止电流优选为1×10-13A以下。

公开(公告)号：US20150279432A1

公开(公告)日：2015-10-01

申请号：US14735350

申请日：2015-06-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Aaron S. Yip ,  Mark A. Helm ,  Ramin Ghodsi

IPC: G11C5/02 ,  G11C5/06

CPC classification number: G11C5/025 ,  G11C5/063 ,  G11C8/08 ,  G11C11/06035 ,  G11C11/06064 ,  G11C11/063 ,  G11C16/02 ,  G11C16/0483 ,  H01L27/11531 ,  H01L27/11573 ,  Y10T29/49069

Abstract: In an embodiment, a memory device includes a stack of tiers of memory cells, a tier of local devices at a level above the stack of tiers of memory cells, and a tier of global devices at substantially a same level as the tier of local devices. A local device may provide selective access to a data line. A global device may provide selective access to a global access line. A tier of memory cells may be selectively coupled to a global access line by the global device of the tier of global devices.

Abstract translation: 在一个实施例中，存储器设备包括层级的存储器单元的堆叠，位于存储器单元的层级之上的层级的本地设备层，以及与本地设备层基本相同的级别的全球设备层 。 本地设备可以提供对数据线的选择性访问。 全局设备可以提供对全局接入线的选择性访问。 一层存储器单元可以由全球设备层的全局设备选择性地耦合到全局接入线路。

公开(公告)号：US09098403B2

公开(公告)日：2015-08-04

申请号：US13749407

申请日：2013-01-24

Applicant: SanDisk Technologies Inc.

Inventor： Steven T. Sprouse ,  Yan Li

IPC: G11C11/00 ,  G06F12/00 ,  G06F12/02 ,  G11C11/56 ,  G11C15/04 ,  G11C16/04 ,  G11C16/34 ,  G11C16/02

CPC classification number: G06F12/0246 ,  G11C11/5642 ,  G11C15/046 ,  G11C16/02 ,  G11C16/0483 ,  G11C16/3459 ,  G11C2211/5641 ,  G11C2211/5642 ,  G11C2213/71 ,  G11C2213/75

Abstract: A NAND Flash based content addressable memory (CAM) is used for a key-value addressed storage drive. The device can use a standard transport protocol such as PCI-E, SAS, SATA, eMMC, SCSI, and so on. A host writes a key-value pair to the drive, where the drive writes the keys along bit lines of a CAM NAND portion of the drive and stores the value in the drive. The drive then maintains a table linking the keys to location of the value. In a read process, the host provides a key to drive, which then broadcasts down the word lines of blocks storing the keys. Based on any matching bit lines, the tables can then be used to retrieve and supply the corresponding data to the host.

Abstract translation: 基于NAND Flash的内容可寻址存储器（CAM）用于键值寻址存储驱动器。 该设备可以使用标准传输协议，如PCI-E，SAS，SATA，eMMC，SCSI等。 主机向驱动器写入键值对，驱动器将驱动器沿着驱动器的CAM NAND部分的位线写入键，并将该值存储在驱动器中。 然后，驱动器维护将键链接到值的位置的表。 在读取过程中，主机提供驱动键，然后将存储键的块的字线广播下来。 基于任何匹配的位线，然后可以使用表来检索并将相应的数据提供给主机。

公开(公告)号：US09009390B2

公开(公告)日：2015-04-14

申请号：US13238749

申请日：2011-09-21

Applicant: Seong Hyeog Choi ,  Hong Rak Son ,  Kyoung Lae Cho ,  Jun Jin Kong ,  Sang Hoon Lee

Inventor： Seong Hyeog Choi ,  Hong Rak Son ,  Kyoung Lae Cho ,  Jun Jin Kong ,  Sang Hoon Lee

IPC: G06F13/00 ,  G06F13/28 ,  G11C16/02 ,  G11C16/06 ,  G11C29/42 ,  G11C16/00 ,  G11C11/56 ,  G11C16/34

CPC classification number: G11C16/02 ,  G06F13/00 ,  G11C11/5642 ,  G11C16/00 ,  G11C16/06 ,  G11C16/3418 ,  G11C16/349 ,  G11C29/42

Abstract: A memory system including a non-volatile memory device and a memory controller is provided. When a read operation on a first data initially output from the non-volatile memory device during a first read operation is successful, the memory controller may change a read voltage for reading a second data stored in the non-volatile memory device during a second read operation.

Abstract translation: 提供了包括非易失性存储器件和存储器控制器的存储器系统。 当在第一次读取操作期间最初从非易失性存储器件输出的第一数据的读取操作成功时，存储器控制器可以在第二次读取期间改变用于读取存储在非易失性存储器件中的第二数据的读取电压 操作。