公开(公告)号：USRE48766E1

公开(公告)日：2021-10-05

申请号：US16703575

申请日：2019-12-04

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Hyoung Seub Rhie

IPC: H01L29/792 ,  H01L27/11556 ,  G11C16/04 ,  G11C16/14 ,  G11C16/26 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582

Abstract: A three-dimensional integrated circuit non-volatile memory array includes a memory array of vertical channel NAND flash strings connected between a substrate source line and upper layer connection lines which each include n-type drain regions and p-type body line contact regions alternately disposed on each side of undoped or lightly doped string body regions so that each NAND flash string includes a vertical string body portion connected to a horizontal string body portion formed from the string body regions of the upper body connection lines.

公开(公告)号：US20210295923A1

公开(公告)日：2021-09-23

申请号：US17224698

申请日：2021-04-07

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Hyoung Seub RHIE

IPC: G11C16/14 ,  G11C16/08 ,  G11C16/04 ,  G11C16/26

Abstract: A non-volatile memory device using existing row decoding circuitry to selectively provide a global erase voltage to at least one selected memory block in order to facilitate erasing of all the non-volatile memory cells of the at least one selected memory block. More specifically, the erase voltage is coupled to the cell body or substrate of memory cells of the at least one selected memory block, where the cell body is electrically isolated from the cell body of non-volatile memory cells in at least one other memory block. By integrating the erase voltage path with the existing row decoding circuitry used to drive row signals for a selected memory block, no additional decoding logic or circuitry is required for providing the erase voltage to the at least one selected memory block.

公开(公告)号：US11082956B2

公开(公告)日：2021-08-03

申请号：US16822139

申请日：2020-03-18

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Khiem Le

IPC: H04W72/04 ,  H04W76/20

Abstract: In one embodiment, a method is performed by a base station in a wireless network. The method includes receiving from a user device a request to reconfigure already-active uplink semi-persistent scheduling (SPS). The already-active uplink SPS grants the user device a resource block allocation (RBA) and a modulation and coding scheme (MCS) for periodic uplink transmissions. The already-active uplink SPS includes a time-interval parameter, the time-interval parameter specifying a time interval between the periodic uplink transmissions. The request includes information related to a proposed adjustment of the time-interval parameter. The method further includes reconfiguring the already-active uplink SPS. The reconfiguring includes modifying the time-interval parameter based, at least in part, on the information.

公开(公告)号：US11049574B2

公开(公告)日：2021-06-29

申请号：US16886977

申请日：2020-05-29

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Jin-Ki Kim ,  Peter B. Gillingham

IPC: G11C16/30 ,  G11C5/14 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/04 ,  G11C16/08

Abstract: A memory device includes core memory such as flash memory for storing data. The memory device includes a first power input to receive a first voltage used to power the flash memory. Additionally, the memory device includes a second power input to receive a second voltage. The memory device includes power management circuitry configured to receive the second voltage and derive one or more internal voltages. The power management circuitry supplies or conveys the internal voltages to the flash memory. The different internal voltages generated by the power management circuitry (e.g., voltage converter circuit) and supplied to the core memory enable operations such as read/program/erase with respect to cells in the core memory.

公开(公告)号：US10944612B2

公开(公告)日：2021-03-09

申请号：US16668218

申请日：2019-10-30

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Hanwu Hu ,  Nima Ahmadvand

IPC: H04L27/26

Abstract: A method includes receiving an Orthogonal Frequency Division Multiplexing (OFDM) signal comprising a plurality of Doppler-shifted OFDM subcarriers and determining frequency-shift data corresponding to the plurality of Doppler-shifted OFDM subcarriers. The determining includes calculating frequency-shift data for each Doppler-shifted OFDM subcarrier of the plurality of Doppler-shifted OFDM subcarriers, thereby yielding a plurality of subcarrier-specific frequency-shift values and calculating an average of the plurality of subcarrier-specific frequency-shift values. The method further includes frequency shifting each subcarrier of the plurality of Doppler-shifted OFDM subcarriers by a value based on the determined frequency-shift data multiplied by a frequency index of each subcarrier.

公开(公告)号：US10923194B2

公开(公告)日：2021-02-16

申请号：US16583352

申请日：2019-09-26

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Chung-Zen Chen ,  Yang-Chieh Lin ,  Chung-Shan Kuo

IPC: G11C16/14 ,  G11C16/16 ,  G11C16/04 ,  G11C16/08 ,  G11C16/02

Abstract: A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.

公开(公告)号：US20200266818A1

公开(公告)日：2020-08-20

申请号：US16795786

申请日：2020-02-20

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Bruce MILLAR

IPC: H03K19/00

Abstract: A system and method of performing off chip drive (OCD) and on-die termination (ODT) are provided. A common pull-up network composed of transistors and a common pull-down network composed of transistors are employed to implement both of these functions. In drive mode, the pull-up network is configured to produce a calibrated drive impedance when an “on” output is to be generated, and the pull-up network is configured to produce a calibrated drive impedance when an “off” output is to be generated. In termination mode, the pull-up network and the pull-down network are configured to produce a calibrated pull-up resistance and pull-down resistance respectively such that together, they form a split termination.

公开(公告)号：US10368307B2

公开(公告)日：2019-07-30

申请号：US16107268

申请日：2018-08-21

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Xuejun Lu ,  Nima Ahmadvand

IPC: H04W52/02 ,  H04W52/26 ,  H04W52/24 ,  H04B17/309 ,  H04W88/08

Abstract: In one embodiment, a method is performed by a wireless station. The method includes receiving from an access point (AP) a request for measurement of at least one link-quality parameter. The method further includes measuring the at least one link-quality parameter to generate a link-quality-parameter measurement. The method also includes determining, for the wireless station, an appropriate wireless-station category of a plurality of wireless-station categories. The plurality of wireless-station categories are defined based at least in part on the link-quality-parameter measurement. In addition, the method includes communicating with the AP in accordance with a transmission schedule corresponding to the plurality of wireless-station categories.

公开(公告)号：US20190214077A1

公开(公告)日：2019-07-11

申请号：US16249482

申请日：2019-01-16

Applicant: Conversant Intellectual Property Management Inc.

Inventor： HakJune OH ,  Hong Beom PYEON ,  Jin-Ki KIM

IPC: G11C11/56 ,  G11C16/34 ,  G11C16/16 ,  G06F1/12 ,  G11C16/26 ,  G11C7/10 ,  G11C16/10

Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

公开(公告)号：US10243542B2

公开(公告)日：2019-03-26

申请号：US15490557

申请日：2017-04-18

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Barry Alan Hoberman ,  Daniel L. Hillman ,  Jon Shiell

IPC: G06F1/32 ,  H02J4/00 ,  H03K3/012 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296

Abstract: Systems and methods manage power in an integrated circuit using power islands. The integrated circuit includes a plurality of power islands wherein a power consumption of each power island within the plurality of power islands is independently controlled within each of the power islands. A power manager determines a target power level for one power island of the plurality of power islands. The power manager then determines an action to change a consumption power level of the one power island of the plurality of power islands to the target power level. The power manager performs the action to change the consumption power level of the one power island of the plurality of power islands to the target power level.