公开(公告)号：US3633184A

公开(公告)日：1972-01-04

申请号：US3633184D

申请日：1969-07-17

Applicant: BELL TELEPHONE LABOR INC

Inventor： HARDING PHILIP A ,  KRAFT GEORGE D

IPC: G11C7/02 ,  G11C11/06

CPC classification number: G11C11/06064

Abstract: The electrical format of a common mode rejection digit circuit for a magnetic memory is changed for reading and writing memory operations by means of multilateral diode bridge switches. A memory word circuit is coupled through memory storage devices to a data digit circuit and two canceling digit circuits associated therewith. The sense of coupling to the canceling circuits is opposite to one another. During writing operations, the data circuit is operated with a canceling circuit which is coupled to the word circuit in opposite sense from the data circuit, and during reading the data circuit is operated with a canceling circuit which is coupled to the word circuit in the same sense as the data circuit to assure equality of opposed shuttle noises in the common mode rejection circuits.

Abstract translation: 用于磁存储器的共模抑制数字电路的电气格式被改变，以便通过多边二极管桥式开关读取和写入存储器操作。 存储器字电路通过存储器存储装置耦合到数据数字电路和与其相关联的两个抵消数字电路。 耦合到消除电路的感觉彼此相反。 在写入操作期间，数据电路以与数据电路相反的字电路耦合的取消电路来操作，并且在读取期间，数据电路与消除电路一起工作，该抵消电路耦合到相同的字电路 感应为数据电路，以确保共模抑制电路中相反的穿梭噪声相等。

公开(公告)号：US3564517A

公开(公告)日：1971-02-16

申请号：US3564517D

申请日：1968-06-24

Applicant: GEN MOTORS CORP

Inventor： MCLEAN WILLIAM E ,  NELSON HAYDEN A ,  RUCH DAVID E

IPC: F02B75/24 ,  G11C11/06 ,  G11C17/02 ,  G11C5/02 ,  G11C17/00

CPC classification number: F02B75/243 ,  G11C11/06064 ,  G11C17/02

Abstract: A COINCIDENT CURRENT MAGNETIC CORE MEMORY COMPRISING A PLURALITY OF CORE MATRICES EACH HAVING A SCRATCH PAD OR ALTERABLE DRO SECTION AND A FIXED NDRO SECTION SHARING CONDUCTORS OF ONE COORDINATE AXIS AND THE SENSE WINDINGS OF EACH MATRIX.

公开(公告)号：US06166944A

公开(公告)日：2000-12-26

申请号：US292986

申请日：1999-04-16

Applicant: Hiroyuki Ogino

Inventor： Hiroyuki Ogino

IPC: G11C11/02 ,  G11C11/06 ,  H01L21/8246 ,  H01L27/105 ,  G11C17/02

CPC classification number: G11C11/06071 ,  G11C11/06064

Abstract: A data storing apparatus in which a magnetic storing means includes magnetic memory cells for memorizing data of a first value or a second value. Input data is written to the memory cells separately or simultaneously by electromagnetic induction. One or more magnetic memory cells are selected, with respect to which the data is to be read or written. Each magnetic memory cell has a ferromagnetic body holding the data of the first value or the second value in accordance with direction of magnetization or magnetizing force thereof. The current control means performs the reading or writing of the data with respect to the selected magnetic cells. The current control means comprises semiconductor devices and controls current therethrough in both directions.

Abstract translation: 一种数据存储装置，其中磁存储装置包括用于存储第一值或第二值的数据的磁存储单元。 输入数据通过电磁感应单独或同时写入存储单元。 选择一个或多个磁存储器单元，相对于哪个数据将被读取或写入。 每个磁存储单元具有铁磁体，其根据其磁化或磁化力的方向保持第一值或第二值的数据。 电流控制装置执行相对于所选择的磁性单元的数据的读取或写入。 电流控制装置包括半导体器件并且控制两个方向上的电流。

公开(公告)号：US3482227A

公开(公告)日：1969-12-02

申请号：US3482227D

申请日：1966-11-25

Applicant: SPERRY RAND CORP

Inventor： ROTHENBERGER ROLAND D ,  KRAUSER JAMES L

IPC: G11C7/02 ,  G11C11/06 ,  G11B5/00 ,  H01P5/12 ,  H04B3/28

CPC classification number: G11C11/06064

公开(公告)号：US09251860B2

公开(公告)日：2016-02-02

申请号：US14735350

申请日：2015-06-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Aaron S. Yip ,  Mark A. Helm ,  Ramin Ghodsi

IPC: G11C16/00 ,  G11C5/02 ,  G11C5/06 ,  G11C16/04

CPC classification number: G11C5/025 ,  G11C5/063 ,  G11C8/08 ,  G11C11/06035 ,  G11C11/06064 ,  G11C11/063 ,  G11C16/02 ,  G11C16/0483 ,  H01L27/11531 ,  H01L27/11573 ,  Y10T29/49069

Abstract: In an embodiment, a memory device includes a stack of tiers of memory cells, a tier of local devices at a level above the stack of tiers of memory cells, and a tier of global devices at substantially a same level as the tier of local devices. A local device may provide selective access to a data line. A global device may provide selective access to a global access line. A tier of memory cells may be selectively coupled to a global access line by the global device of the tier of global devices.

公开(公告)号：US09070442B2

公开(公告)日：2015-06-30

申请号：US14013370

申请日：2013-08-29

Applicant: Micron Technology, Inc.

Inventor： Aaron S. Yip ,  Mark A. Helm ,  Ramin Ghodsi

IPC: G11C16/00 ,  G11C16/02 ,  G11C11/063 ,  G11C11/06 ,  G11C5/02

CPC classification number: G11C5/025 ,  G11C5/063 ,  G11C8/08 ,  G11C11/06035 ,  G11C11/06064 ,  G11C11/063 ,  G11C16/02 ,  G11C16/0483 ,  H01L27/11531 ,  H01L27/11573 ,  Y10T29/49069

Abstract: In an embodiment, a memory device includes a stack of tiers of memory cells, a tier of local devices at a level above the stack of tiers of memory cells, and a tier of global devices at substantially a same level as the tier of local devices. A local device may provide selective access to a data line. A global device may provide selective access to a global access line. A tier of memory cells may be selectively coupled to a global access line by the global device of the tier of global devices.

Abstract translation: 在一个实施例中，存储器设备包括层级的存储器单元的堆叠，位于存储器单元的层级之上的层级的本地设备层，以及与本地设备层基本相同的级别的全球设备层 。 本地设备可以提供对数据线的选择性访问。 全局设备可以提供对全局接入线的选择性访问。 一层存储器单元可以由全球设备层的全局设备选择性地耦合到全局接入线路。

公开(公告)号：US20150063024A1

公开(公告)日：2015-03-05

申请号：US14013370

申请日：2013-08-29

Applicant: Micron Technology, Inc.

Inventor： Aaron S. YIP ,  Mark A. HELM ,  Ramin GHODSI

IPC: G11C16/02

CPC classification number: G11C5/025 ,  G11C5/063 ,  G11C8/08 ,  G11C11/06035 ,  G11C11/06064 ,  G11C11/063 ,  G11C16/02 ,  G11C16/0483 ,  H01L27/11531 ,  H01L27/11573 ,  Y10T29/49069

Abstract: In an embodiment, a memory device includes a stack of tiers of memory cells, a tier of local devices at a level above the stack of tiers of memory cells, and a tier of global devices at substantially a same level as the tier of local devices. A local device may provide selective access to a data line. A global device may provide selective access to a global access line. A tier of memory cells may be selectively coupled to a global access line by the global device of the tier of global devices.

公开(公告)号：US4047164A

公开(公告)日：1977-09-06

申请号：US611227

申请日：1975-09-08

Applicant: Michael F. Boice

Inventor： Michael F. Boice

IPC: G11C11/06 ,  G11C11/02

CPC classification number: G11C11/06064

Abstract: A read and write drive system is disclosed for a 21/2D coincident current magnetic core memory of the type in which for each word bit, bit lines threaded through the magnetic cores are arranged in a matrix of M groups, each of N bit lines. The drive system includes for the bit line matrix of each word bit a separate set of M write drive switches, and for n matrices of n different word bits, wherein n .gtoreq. 2, M read sink switches, N read drive switches and N write sink switches. These switches are used to apply 1/2 drive current through selected bit lines, during the read operation, to read out the n word bits of a selected word and to apply 1/2 drive current to independently store either a binary 1 or a binary 0 in each of the n word bits. The total number of switches, required for n word bits, is M(n+1) + 2N switches.

Abstract translation: 公开了一种读/写驱动系统，用于21 / 2D重合当前磁芯存储器，其中对于每个字位，穿过磁芯的位线被排列成M组的矩阵，每个N位线。 驱动系统包括每个字位的位线矩阵单独的一组M写驱动开关，以及n个不同字位的n个矩阵，其中n> / = 2，M读宿开关，N读驱动开关和N 写水槽开关 这些开关用于在读取操作期间通过所选位线施加1/2驱动电流，以读出所选字的n个字位，并施加1/2驱动电流以独立存储二进制1或二进制 每个n个字位中有0个。 n个字位所需的开关总数为M（n + 1）+ 2N个开关。

公开(公告)号：US20150279432A1

公开(公告)日：2015-10-01

申请号：US14735350

申请日：2015-06-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Aaron S. Yip ,  Mark A. Helm ,  Ramin Ghodsi

IPC: G11C5/02 ,  G11C5/06

CPC classification number: G11C5/025 ,  G11C5/063 ,  G11C8/08 ,  G11C11/06035 ,  G11C11/06064 ,  G11C11/063 ,  G11C16/02 ,  G11C16/0483 ,  H01L27/11531 ,  H01L27/11573 ,  Y10T29/49069

Abstract: In an embodiment, a memory device includes a stack of tiers of memory cells, a tier of local devices at a level above the stack of tiers of memory cells, and a tier of global devices at substantially a same level as the tier of local devices. A local device may provide selective access to a data line. A global device may provide selective access to a global access line. A tier of memory cells may be selectively coupled to a global access line by the global device of the tier of global devices.

Abstract translation: 在一个实施例中，存储器设备包括层级的存储器单元的堆叠，位于存储器单元的层级之上的层级的本地设备层，以及与本地设备层基本相同的级别的全球设备层 。 本地设备可以提供对数据线的选择性访问。 全局设备可以提供对全局接入线的选择性访问。 一层存储器单元可以由全球设备层的全局设备选择性地耦合到全局接入线路。

公开(公告)号：US4096583A

公开(公告)日：1978-06-20

申请号：US732928

申请日：1976-10-15

Applicant: Kurt Wright ,  Thomas J. Gilligan

Inventor： Kurt Wright ,  Thomas J. Gilligan

IPC: G11C11/02 ,  G11C11/06 ,  H03K5/02

CPC classification number: G11C11/06078 ,  G11C11/06064 ,  H03K5/02

Abstract: A large, 2 wire, 21/2D core memory includes four, 1K (1024) by 1280, core frames with 1280 Y conductors each stringing and inductively coupling a column of 1024 cores in each of the four frames and 4K orthogonal X conductors each stringing and inductively coupling one row of 1280 cores. A word position within the memory is defined by 5 pairs of Y conductors, a corresponding X conductor from each frame, and selection of relative current directions in the Y conductors. Reading of a 20 bit word is accomplished with 5 sense amplifiers in four rapid succession read sub-operations. Writing is accomplished in two sub-operations by separately controlling partial select digit currents in each of the 5 pairs of Y conductors. A bidirectional X drive and switching arrangement utilizes overlapping X drive currents and shared circuitry to maximize memory speed and reduce electronic components costs.

Abstract translation: 一个大的2线，21 / 2D核心存储器包括四个1K（1024）×1280，具有1280个Y导体的核心帧，每个引线和电感耦合四个帧中的每一个1024个核心的列和每个串行的4K个正交X导体 并感应耦合一行1280个内核。 存储器中的字位置由5对Y导体，来自每个帧的相应X导体以及Y导体中相对电流方向的选择来定义。 在四个快速连续读取子操作中，使用5个读出放大器来读取20位字。 通过分别控制5对Y导体中的每一个中的部分选择数字电流，在两个子操作中完成写入。 双向X驱动器和开关装置利用重叠的X驱动电流和共享电路来最大化存储器速度并降低电子元件成本。