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    Early noise pulse and long duration, stabilized switching pulse
    3.
    发明授权
    Early noise pulse and long duration, stabilized switching pulse 失效
    早期噪声脉冲和长时间，稳定的开关脉冲

    公开(公告)号：US4133050A

    公开(公告)日：1979-01-02

    申请号：US793031

    申请日：1977-05-02

    Applicant: Victor L. Sell

    Inventor： Victor L. Sell

    IPC: G11C11/06 ,  G11C11/063

    CPC classification number: G11C11/06007

    Abstract: A large bit size core memory which maximizes usable flux includes at least one array of low drive toroidal magnetic memory cores, a sense-inhibit conductor pair passing through the array in a given direction to inductively couple all cores in the array, a plurality of perpendicular drive conductors, each passing through the array perpendicular to the sense-inhibit conductor pair and inductively coupling a portion of the cores in the array, a plurality of parallel drive conductors, each passing through the array parallel to the sense-inhibit conductor pair and inductively coupling a portion of the cores in the array, and driving and switching circuitry coupled to drive selected a core during a read portion of a memory cycle with a current which rapidly increases to approximately provide the coercive force MMF to the core and then increases relatively slowly toward the full drive current. The resulting core output switching pulse received by a strobed sense amplifier has an early noise component from delta noise and coupling noise and a subsequent logic 1 switching pulse which is extremely stable with respect to normal variations in temperature and drive current, which has a flat, low magnitude peak that satisfies sense amplifier requirements and which is sufficiently delayed to permit attenuation of the noise signals.

    Read/write structures for a three dimensional memory
    4.
    发明授权
    Read/write structures for a three dimensional memory 有权
    三维存储器的读/写结构

    公开(公告)号：US08164940B2

    公开(公告)日：2012-04-24

    申请号：US12638627

    申请日：2009-12-15

    Applicant: Ozhan Ozatay ,  Bruce D. Terris

    Inventor： Ozhan Ozatay ,  Bruce D. Terris

    IPC: G11C11/063

    CPC classification number: H01L27/222 ,  G11C5/02 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C19/0808

    Abstract: Read/write structures for three-dimensional memories are disclosed. In one embodiment, a three-dimensional memory includes a plurality of data storage layers fabricated in parallel on top of one another to form a three-dimensional structure. Each data storage layer is able to store bits of data in the form of magnetic domains. The memory further includes a column of write elements that is operable to write a column of magnetic domains to the first data storage layer representing a column of bits. The first data storage layer is patterned into a plurality of magnetic conductors aligned transverse to the column of write elements. A control system may inject spin-polarized current pulses in the magnetic conductors to transfer the column of magnetic domains laterally within the first data storage layer. The control system may transfer of the column of magnetic domains perpendicularly from the first data storage layer to another data storage layer.

    Abstract translation: 公开了用于三维存储器的读/写结构。 在一个实施例中，三维存储器包括彼此之上并行制造的多个数据存储层，以形成三维结构。 每个数据存储层能够存储磁畴形式的数据位。 存储器还包括写入元件列，其可操作以将磁畴列写入表示位列的第一数据存储层。 将第一数据存储层图案化成横向于写入元件列的多个磁性导体。 控制系统可以在磁导体中注入自旋极化电流脉冲，以在第一数据存储层内横向磁转移磁畴列。 控制系统可以将磁畴列从第一数据存储层垂直传送到另一个数据存储层。

    Semiconductor memory device
    5.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US07573757B2

    公开(公告)日：2009-08-11

    申请号：US12073294

    申请日：2008-03-04

    Applicant: Sung-Joo Ha ,  Ho-Youb Cho

    Inventor： Sung-Joo Ha ,  Ho-Youb Cho

    IPC: G11C11/063

    CPC classification number: G11C7/1078 ,  G11C7/1048 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/1096

    Abstract: Disclosed herein is a semiconductor memory device for reducing a current consumption used for operating a write command or a read command. The semiconductor memory device includes a global data latch unit for latching a global data loaded on a global data line in response to a first write enable signal to thereby generate a global latch data; a local data write driving unit for receiving the global latch data to output a local data to a local data line in response to a second write enable signal; and a write driver control unit for generating the first write enable signal and the second write enable signal to inactivate the first write enable signal when a write operation is not performed.

    Abstract translation: 这里公开了一种用于减少用于操作写入命令或读取命令的电流消耗的半导体存储器件。 半导体存储器件包括全局数据锁​​存单元，用于响应于第一写使能信号来锁存加载在全局数据线上的全局数据，从而生成全局锁存数据; 本地数据写驱动单元，用于接收全局锁存数据，以响应于第二写使能信号将本地数据输出到本地数据线; 以及写入驱动器控制单元，用于在不执行写入操作时产生第一写入使能信号和第二写入使能信号以使第一写入使能信号失活。

    Nonvolatile memory element composed of combined superconductor ring and MOSFET
    6.
    发明授权
    Nonvolatile memory element composed of combined superconductor ring and MOSFET 失效
    由组合超导体环和MOSFET组成的非易失性存储元件

    公开(公告)号：US5332722A

    公开(公告)日：1994-07-26

    申请号：US028632

    申请日：1993-03-08

    Applicant: Mitsuka Fujihira

    Inventor： Mitsuka Fujihira

    IPC: G11C11/44 ,  H01L29/82 ,  G11C11/063 ,  H01L27/18

    CPC classification number: G11C11/44 ,  H01L29/82 ,  Y10S505/831 ,  Y10S505/833 ,  Y10S505/841

    Abstract: A novel nonvolatile memory element or cell comprising a memory means consisting of at least one superconducting ring (21, 22) and a detector means consisting of a MOSFET. The superconducting ring and the MOSFET are arranged in such a manner that a magnetic flux created by the superconducting ring (21, 22) passes through a channel zone of the MOSFET. Information is held in the superconducting ring in a form of permanent current and is detected electrically as variation in the conductivity of the channel zone of the MOSFET.

    Abstract translation: 一种新颖的非易失性存储元件或单元，包括由至少一个超导环（21,22）和由MOSFET组成的检测器装置构成的存储器件。 超导环和MOSFET以由超导环（21,22）产生的磁通通过MOSFET的沟道区的方式排列。 信息以永久电流的形式保存在超导环中，并且被电性地检测为MOSFET的沟道区的导电性的变化。

    READ/WRITE STRUCTURES FOR A THREE DIMENSIONAL MEMORY
    8.
    发明申请
    READ/WRITE STRUCTURES FOR A THREE DIMENSIONAL MEMORY 有权
    三维存储器的读/写结构

    公开(公告)号：US20110141792A1

    公开(公告)日：2011-06-16

    申请号：US12638627

    申请日：2009-12-15

    Applicant: Ozhan Ozatay ,  Bruce D. Terris

    Inventor： Ozhan Ozatay ,  Bruce D. Terris

    IPC: G11C11/063 ,  H01L43/12

    CPC classification number: H01L27/222 ,  G11C5/02 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C19/0808

    Abstract: Read/write structures for three-dimensional memories are disclosed. In one embodiment, a three-dimensional memory includes a plurality of data storage layers fabricated in parallel on top of one another to form a three-dimensional structure. Each data storage layer is able to store bits of data in the form of magnetic domains. The memory further includes a column of write elements that is operable to write a column of magnetic domains to the first data storage layer representing a column of bits. The first data storage layer is patterned into a plurality of magnetic conductors aligned transverse to the column of write elements. A control system may inject spin-polarized current pulses in the magnetic conductors to transfer the column of magnetic domains laterally within the first data storage layer. The control system may transfer of the column of magnetic domains perpendicularly from the first data storage layer to another data storage layer.

    Abstract translation: 公开了用于三维存储器的读/写结构。 在一个实施例中，三维存储器包括彼此之上并行制造的多个数据存储层，以形成三维结构。 每个数据存储层能够存储磁畴形式的数据位。 存储器还包括写入元件列，其可操作以将磁畴列写入表示位列的第一数据存储层。 将第一数据存储层图案化成横向于写入元件列的多个磁性导体。 控制系统可以在磁导体中注入自旋极化电流脉冲，以在第一数据存储层内横向磁转移磁畴列。 控制系统可以将磁畴列从第一数据存储层垂直传送到另一个数据存储层。

    Semiconductor memory devices having variable additive latency
    9.
    发明授权
    Semiconductor memory devices having variable additive latency 有权
    具有可变添加剂延迟的半导体存储器件

    公开(公告)号：US07590013B2

    公开(公告)日：2009-09-15

    申请号：US11711647

    申请日：2007-02-28

    Applicant: So-Young Yu ,  Jae-Kyung Lee

    Inventor： So-Young Yu ,  Jae-Kyung Lee

    IPC: G11C11/063

    CPC classification number: G11C7/22 ,  G11C7/1045 ,  G11C2207/2272

    Abstract: A semiconductor memory device includes an additive latency setting unit configured to receive a mode setting code from an external unit in response to the mode setting signal during a mode setting operation, set an additive latency value in response to the mode setting code, and receive the mode setting code in response to the additive latency setting signal during a normal operation, and an additive latency changing unit configured to change the additive latency value in response to the mode setting code during the normal operation.

    Abstract translation: 一种半导体存储器件，包括：附加延迟设置单元，被配置为在模式设置操作期间响应于模式设置信号从外部单元接收模式设置代码，响应于模式设置代码设置加法延迟值，并且接收 响应于在正常操作期间的附加延迟设置信号的模式设置代码，以及附加等待时间改变单元，被配置为在正常操作期间响应于模式设置代码来改变添加等待时间值。

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