公开(公告)号：US11960320B2

公开(公告)日：2024-04-16

申请号：US18301669

申请日：2023-04-17

Applicant: KIOXIA CORPORATION

Inventor： Toshitada Saito ,  Akihisa Fujimoto

IPC: H03L7/07 ,  G06F1/06 ,  G06F1/12 ,  G06F13/38 ,  G06F13/42 ,  H03L7/00 ,  H03L7/08 ,  H03L7/091 ,  H03L7/099 ,  H04L7/00 ,  H04L7/033 ,  H04L25/08 ,  H04L25/14

CPC classification number: G06F1/06 ,  G06F1/12 ,  G06F13/38 ,  G06F13/4282 ,  H03L7/00 ,  H03L7/07 ,  H03L7/0807 ,  H03L7/091 ,  H03L7/099 ,  H04L7/0004 ,  H04L7/033 ,  H04L25/085 ,  H04L25/14 ,  H04L7/0012

Abstract: According to one embodiment, an interface system includes a receiver, a first clock generator, a second clock generator, and a sampling circuit. The receiver is configured to receive a first clock and serial data from a host. The first clock generator includes a first voltage controlled oscillator (VCO) and is configured to generate a second clock on the basis of the first clock. The second clock generator includes a second voltage controlled oscillator (VCO) and is configured to generate a third clock on the basis of the serial data. The sampling circuit is configured to sample reception data on the basis of the third clock and the serial data.

公开(公告)号：US11656651B2

公开(公告)日：2023-05-23

申请号：US17885925

申请日：2022-08-11

Applicant: Kioxia Corporation

Inventor： Toshitada Saito ,  Akihisa Fujimoto

IPC: H03L7/07 ,  G06F1/06 ,  H04L7/00 ,  H04L7/033 ,  H03L7/091 ,  H03L7/00 ,  H04L25/08 ,  H04L25/14 ,  G06F1/12 ,  G06F13/38 ,  G06F13/42 ,  H03L7/08 ,  H03L7/099

CPC classification number: G06F1/06 ,  G06F1/12 ,  G06F13/38 ,  G06F13/4282 ,  H03L7/00 ,  H03L7/07 ,  H03L7/0807 ,  H03L7/091 ,  H03L7/099 ,  H04L7/0004 ,  H04L7/033 ,  H04L25/085 ,  H04L25/14 ,  H04L7/0012

Abstract: According to one embodiment, an interface system includes a receiver, a first clock generator, a second clock generator, and a sampling circuit. The receiver is configured to receive a first clock and serial data from a host. The first clock generator includes a first voltage controlled oscillator (VCO) and is configured to generate a second clock on the basis of the first clock. The second clock generator includes a second voltage controlled oscillator (VCO) and is configured to generate a third clock on the basis of the serial data. The sampling circuit is configured to sample reception data on the basis of the third clock and the serial data.

公开(公告)号：US11460878B2

公开(公告)日：2022-10-04

申请号：US17375054

申请日：2021-07-14

Applicant: Kioxia Corporation

Inventor： Toshitada Saito ,  Akihisa Fujimoto

IPC: H03L7/07 ,  G06F1/06 ,  H04L7/00 ,  H04L7/033 ,  H03L7/091 ,  H03L7/00 ,  H04L25/08 ,  H04L25/14 ,  G06F1/12 ,  G06F13/38 ,  G06F13/42 ,  H03L7/08 ,  H03L7/099

Abstract: According to one embodiment, an interface system includes a receiver, a first clock generator, a second clock generator, and a sampling circuit. The receiver is configured to receive a first clock and serial data from a host. The first clock generator includes a first voltage controlled oscillator (VCO) and is configured to generate a second clock on the basis of the first clock. The second clock generator includes a second voltage controlled oscillator (VCO) and is configured to generate a third clock on the basis of the serial data. The sampling circuit is configured to sample reception data on the basis of the third clock and the serial data.

公开(公告)号：US12228960B2

公开(公告)日：2025-02-18

申请号：US18601440

申请日：2024-03-11

Applicant: KIOXIA CORPORATION

Inventor： Toshitada Saito ,  Akihisa Fujimoto

IPC: G06F1/06 ,  G06F1/12 ,  G06F13/38 ,  G06F13/42 ,  H03L7/00 ,  H03L7/07 ,  H03L7/08 ,  H03L7/091 ,  H03L7/099 ,  H04L7/00 ,  H04L7/033 ,  H04L25/08 ,  H04L25/14

Abstract: According to one embodiment, an interface system includes a receiver, a first clock generator, a second clock generator, and a sampling circuit. The receiver is configured to receive a first clock and serial data from a host. The first clock generator includes a first voltage controlled oscillator (VCO) and is configured to generate a second clock on the basis of the first clock. The second clock generator includes a second voltage controlled oscillator (VCO) and is configured to generate a third clock on the basis of the serial data. The sampling circuit is configured to sample reception data on the basis of the third clock and the serial data.

公开(公告)号：US12141091B2

公开(公告)日：2024-11-12

申请号：US18364970

申请日：2023-08-03

Applicant: KIOXIA CORPORATION

Inventor： Kunihiko Yamagishi ,  Toshitada Saito

IPC: G06F13/42 ,  G06F12/02 ,  G06F13/38 ,  G06F13/40 ,  H04L25/03

Abstract: A semiconductor device capable of communicating with a host apparatus includes a symbol generation unit, a coding unit, and a transmission unit. The symbol generation unit includes a random number generation circuit and generates a symbol according to a random number generated by the random number generation circuit. The coding unit performs 8b/10b coding for the symbol. The transmission unit transmits the symbol coded by the 8b/10b coding unit to the host apparatus.

公开(公告)号：US11977940B2

公开(公告)日：2024-05-07

申请号：US17369449

申请日：2021-07-07

Applicant: Kioxia Corporation

Inventor： Akihisa Fujimoto ,  Toshitada Saito ,  Noriya Sakamoto ,  Atsushi Kondo

IPC: G11C5/02 ,  G06K19/077 ,  G11C5/06 ,  G11C11/4074 ,  G11C16/02 ,  G11C16/30

CPC classification number: G06K19/07732 ,  G06K19/07733 ,  G06K19/07743 ,  G11C5/06 ,  G11C11/4074 ,  G11C16/02 ,  G11C16/30

Abstract: According to one embodiment, there is provided a memory card including a first surface, a second surface, and 1st to Nth terminal groups. The first surface includes first to Nth rows, where N is an integer of two or greater. The second surface faces the opposite side from the first surface. The 1st to Nth terminal groups are placed in the first to Nth rows. The 1st terminal group includes terminals to which differential clock signals are assigned, terminals to which single-ended signals are assigned, and a terminal to which a first power supply voltage is assigned. Kth terminal group, where K is an integer no smaller than two and no greater than N, includes terminals to which differential data signals are assigned.

公开(公告)号：US11762800B2

公开(公告)日：2023-09-19

申请号：US17500581

申请日：2021-10-13

Applicant: Kioxia Corporation

Inventor： Kunihiko Yamagishi ,  Toshitada Saito

IPC: G06F13/42 ,  G06F13/40 ,  G06F13/38 ,  H04L25/03 ,  G06F12/02

CPC classification number: G06F13/4068 ,  G06F12/0246 ,  G06F13/385 ,  G06F13/40 ,  G06F13/4063 ,  G06F13/42 ,  G06F13/4282 ,  H04L25/03828 ,  G06F2212/7201 ,  G06F2213/3804 ,  G06F2213/3854

Abstract: A semiconductor device capable of communicating with a host apparatus includes a symbol generation unit, a coding unit, and a transmission unit. The symbol generation unit includes a random number generation circuit and generates a symbol according to a random number generated by the random number generation circuit. The coding unit performs 8b/10b coding for the symbol. The transmission unit transmits the symbol coded by the 8b/10b coding unit to the host apparatus.

公开(公告)号：US11093811B2

公开(公告)日：2021-08-17

申请号：US16619012

申请日：2018-03-09

Applicant: Kioxia Corporation

Inventor： Akihisa Fujimoto ,  Toshitada Saito ,  Noriya Sakamoto ,  Atsushi Kondo

IPC: G06F13/00 ,  G06K19/077

Abstract: A memory card includes a first surface, a second surface, and 1st to Nth terminal groups. The first surface includes first to Nth rows, wherein N is an integer of two or greater. The second surface faces the opposite side from the first surface. The 1st to Nth terminal groups are placed in the first to Nth rows. The 1st terminal group includes terminals to which differential clock signals are assigned, terminals to which single-ended signals are assigned, and a terminal to which a first power supply voltage is assigned. Kth terminal group, wherein K is an integer no smaller than two and no greater than N, includes terminals to which differential data signals are assigned.