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公开(公告)号:US12093202B2
公开(公告)日:2024-09-17
申请号:US18079001
申请日:2022-12-12
发明人: Yung-Sheng Fang , Igor Elkanovich , Pei Yu
IPC分类号: G06F13/40
CPC分类号: G06F13/40
摘要: The disclosure provides a data bus inversion (DBI) encoding device and a DBI encoding method. The DBI encoding device includes a comparator circuit, a first controllable inverting circuit and a second controllable inverting circuit. The comparator circuit checks the number of the different bits between a first raw data and a second raw data. Based on the number of the different bits, the first controllable inversion circuit determines whether to invert a first DBI bit corresponding to the first raw data as a second DBI bit corresponding to the second raw data. The second controllable inversion circuit determines, based on the second DBI bit, whether to adopt the second raw data as a second encoded data corresponding to the second raw data, or invert the second raw data to generate the second encoded data.
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公开(公告)号:US20240264018A1
公开(公告)日:2024-08-08
申请号:US18164154
申请日:2023-02-03
发明人: Matthew Moe , Youngbae Park , Robert Wilcox , Richard Hibbs
CPC分类号: G01L5/0052 , G01R1/06727 , G06F13/40 , H01R11/01 , H05K5/0018 , H05K5/0204 , G06F2213/0026
摘要: A contact force sensing device may be configured to mate with a port connector having a plurality of conductive contact structures. The contact force sensing device may include a base and a force sensor on the base. The force sensor may be configured to measure a force applied by a first conductive contact structure in the plurality of conductive contact structures using a sensor probe that contacts the first conductive contact structure when the sensor probe is inserted into the port connector. The contact force sensing device may include a mating connector surrogate structure that flanks the sensor probe and is configured to contact at least a second conductive contact structure in the plurality of conductive contact structures when the sensor probe contacts the first conductive contact structure.
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公开(公告)号:US11886624B2
公开(公告)日:2024-01-30
申请号:US17473137
申请日:2021-09-13
发明人: Ingoo Heo , Youngwook Noh
CPC分类号: G06F21/79 , G06F13/40 , G06F21/602 , G06F21/72 , G09C1/00 , H04L9/065 , H04L9/0631 , H04L9/0637 , H04L9/0869 , G06F13/1668 , H04L2209/122
摘要: A writing method of a crypto device includes receiving a write request from a central processing unit, determining a write attribute of the write request, and performing one of a partial write operation and a full write operation according to the write attribute. In the full write operation, a random number for a version count is generated, a key stream is generated using the version count, the key stream and write data are encrypted in a first logical operation, and the encrypted data and the version count are stored in a memory device.
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公开(公告)号:US11854654B2
公开(公告)日:2023-12-26
申请号:US17392452
申请日:2021-08-03
发明人: Lee D. Whetsel
IPC分类号: G11C7/10 , G01R31/3185 , G06F13/40 , G06F13/42 , G06F3/06 , G06F13/38 , H04L67/1097
CPC分类号: G11C7/1036 , G01R31/318572 , G06F13/40 , G06F13/4022 , G06F13/4291 , G11C7/1066 , G06F3/0601 , G06F13/385 , H04L67/1097
摘要: A two pin communication interface bus and control circuits are used with circuit boards, integrated circuits, or embedded cores within integrated circuits. One pin carries data bi-directionally and address and instruction information from a controller to a selected port. The other pin carries a clock signal from the controller to a target port or ports in or on the desired circuit or circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is minimal. The bus is used for communication, such as serial communication related to the functional operation of an IC or core design, or serial communication related to test, emulation, debug, and/or trace operations of an IC or core design.
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公开(公告)号:US20230376440A1
公开(公告)日:2023-11-23
申请号:US18364970
申请日:2023-08-03
申请人: KIOXIA CORPORATION
CPC分类号: G06F13/4068 , G06F13/4063 , G06F13/42 , G06F13/385 , G06F12/0246 , G06F13/40 , G06F13/4282 , H04L25/03828 , G06F2213/3854 , G06F2212/7201 , G06F2213/3804
摘要: A semiconductor device capable of communicating with a host apparatus includes a symbol generation unit, a coding unit, and a transmission unit. The symbol generation unit includes a random number generation circuit and generates a symbol according to a random number generated by the random number generation circuit. The coding unit performs 8b/10b coding for the symbol. The transmission unit transmits the symbol coded by the 8b/10b coding unit to the host apparatus.
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公开(公告)号:US20180307263A1
公开(公告)日:2018-10-25
申请号:US15960074
申请日:2018-04-23
申请人: INTEL CORPORATION
CPC分类号: G06F1/08 , G06F1/12 , G06F13/40 , G06F13/4291 , H04J3/0697
摘要: The present disclosure provides devices and techniques to dynamically change the operating frequency of an interface where components on the interface have non-common clocks. An interface component may be provided with a frequency negotiation component to negotiate a shift in an operating frequency with other component on an interface where the different components have non-common clocks.
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公开(公告)号:US20180294016A1
公开(公告)日:2018-10-11
申请号:US16003780
申请日:2018-06-08
发明人: Lee D. Whetsel
CPC分类号: G11C7/1036 , G01R31/318572 , G06F3/0601 , G06F13/385 , G06F13/40 , G06F13/4022 , G06F13/4291 , G11C7/1066 , H04L29/08549 , H04L67/1097
摘要: A two pin communication interface bus and control circuits are used with circuit boards, integrated circuits, or embedded cores within integrated circuits. One pin carries data bi-directionally and address and instruction information from a controller to a selected port. The other pin carries a clock signal from the controller to a target port or ports in or on the desired circuit or circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is minimal. The bus is used for communication, such as serial communication related to the functional operation of an IC or core design, or serial communication related to test, emulation, debug, and/or trace operations of an IC or core design.
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公开(公告)号:US20180276168A1
公开(公告)日:2018-09-27
申请号:US15762035
申请日:2015-12-11
发明人: Shih Chuan HUANG , Yu Cheng WU , Chih Sheng LIAO , Hsin Wen HSU , Benjiman WHITE , William E. HERTLING , Mike WHITMARSH
IPC分类号: G06F13/40
CPC分类号: G06F13/4068 , G06F1/181 , G06F13/14 , G06F13/38 , G06F13/40
摘要: Example implementations relate to computing devices with movable input/output (I/O) connectors. For example, a computing device may include a chassis of the computing device and an I/O connector to connect an I/O device to the computing device. The I/O connector may be movable about an axis relative to the chassis by at least 180 degrees such that the I/O connector is accessible from multiple sides of the chassis.
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公开(公告)号:US20180224912A1
公开(公告)日:2018-08-09
申请号:US15748414
申请日:2016-01-06
发明人: Po-Lan Wang , Jen-Chun Hsu , Yi-Feng Lin
CPC分类号: G06F1/266 , G06F1/28 , G06F1/305 , G06F13/24 , G06F13/38 , G06F13/40 , G06F13/4282 , G06F2213/0042
摘要: Example implementations relate to detection circuits. In one example, a detection circuit includes a power supply, a transistor coupled to the power supply, a port coupled via the transistor to the power supply, where the port is to transmit power received via the transistor from the power supply to a corresponding port included in an external device when the corresponding port is coupled to the port, and a detection circuit to detect a voltage between the port and the corresponding port when the port is coupled to the corresponding port and interrupt, via the transistor, power supplied to the port when the detected voltage satisfies a threshold voltage.
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公开(公告)号:US10033429B2
公开(公告)日:2018-07-24
申请号:US15637623
申请日:2017-06-29
发明人: Zixin Wu
CPC分类号: H04B1/525 , G06F13/40 , H03K19/00346 , H04B3/23 , H04B3/32 , H04L25/0278 , H04L25/0292
摘要: Disclosed is a signal transmitting circuit, a retiming unit is connected with an aggressor signal line to output a previous moment signal and a current moment signal, a control signal associated with the previous moment signal and the current moment signal is output to a crosstalk compensation circuit through a logic circuit, the crosstalk compensation circuit receives a signal from a victim signal line, so as to dynamically change delays corresponding to different transmission modes in combination with inputs of the victim signal line and the aggressor signal line.
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