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    Information processing apparatus
    1.
    发明授权
    Information processing apparatus 有权

    公开(公告)号：US12197261B2

    公开(公告)日：2025-01-14

    申请号：US17931710

    申请日：2022-09-13

    Applicant: Kioxia Corporation

    Inventor： Akihisa Fujimoto ,  Atsushi Kondo

    IPC: G06F1/26 ,  G11C5/14 ,  G11C16/04 ,  G11C16/30 ,  H02M3/04

    Abstract: According to one embodiment, an information processing apparatus includes a connecting portion connectable to a removable memory device and a power supply circuit configured to apply a first voltage and a second voltage to the removable memory device. When the removable memory device is connected to the connecting portion, one of a pair of first feedback wires is electrically connected to one of the first power supply terminals to which the first voltage is applicable, and the other of the pair of first feedback wires is electrically connected to one of the power supply ground terminals connectable to a ground level, the power supply circuit is configured to control the first voltage, based on a voltage between the pair of first feedback wires.

    Memory device and controlling method of the same
    3.
    再颁专利
    Memory device and controlling method of the same 有权

    公开(公告)号：USRE49921E1

    公开(公告)日：2024-04-16

    申请号：US17377952

    申请日：2021-07-16

    Applicant: KIOXIA CORPORATION

    Inventor： Akihisa Fujimoto

    IPC: G06F12/00 ,  G06F12/02 ,  G06F13/00 ,  G06F13/28

    CPC classification number: G06F12/0246 ,  G06F2212/7202

    Abstract: A memory device includes a memory which has memory areas, and a controller has a first mode and a second mode. Upon receipt of write data, the controller writes data in the memory areas while managing correspondence between logical addresses of write data and memory areas which store corresponding write data. A plurality of the memory areas constitutes a management unit. The controller in the first mode is able to write pieces of data in respective memory areas and configured to maintain data in memory areas in one management unit which contains data to be updated. The controller in the second mode writes pieces of data in respective memory areas in the ascending order of logical addresses of the pieces of data and invalidates data in memory areas in one management unit which contains updated data.

    Card and host device
    6.
    再颁专利
    Card and host device 有权

    公开(公告)号：USRE49643E1

    公开(公告)日：2023-09-05

    申请号：US17477045

    申请日：2021-09-16

    Applicant: KIOXIA CORPORATION

    Inventor： Akihisa Fujimoto

    IPC: G06F3/06 ,  G11C5/14 ,  H04L1/00

    CPC classification number: G06F3/0679 ,  G06F3/061 ,  G06F3/0604 ,  G06F3/0608 ,  G06F3/0659 ,  G11C5/143 ,  H04L1/0061 ,  G06F2003/0697 ,  G06F2206/1014 ,  H04L2001/0094

    Abstract: A host device is configured to read and write information from and into a card and to supply a supply voltage that belongs to a first voltage range or a second voltage range which is lower than the first voltage range, and issues a voltage identification command to the card. The voltage identification command includes a voltage range identification section, an error detection section, and a check pattern section. The voltage range identification section includes information indicating which one of the first voltage range and the second voltage range the supply voltage belongs. The error detection section has a pattern configured to enable the card which has received the voltage identification command to detect errors in the voltage identification command. The check pattern section has a preset pattern.

    Memory device and host device
    7.
    发明授权
    Memory device and host device 有权

    公开(公告)号：US11573701B2

    公开(公告)日：2023-02-07

    申请号：US17196390

    申请日：2021-03-09

    Applicant: Kioxia Corporation

    Inventor： Akihisa Fujimoto

    IPC: G06F3/06 ,  G06F12/02 ,  G06F13/42

    Abstract: According to one embodiment, a memory device includes a nonvolatile semiconductor memory having physical storage areas that includes a user area externally accessible and are divided into management units and a control unit. The control unit receives a control command having a first argument to designate a sequential write area and a read command or a write command, assigns a management unit represented by an address of the read command or the write command as the sequential write area, and changes memory access control by judging whether an address of a memory access command to access the user area indicates access in the sequential write area whose size is equivalent to the management unit.

    Interface system
    8.
    发明授权
    Interface system 有权

    公开(公告)号：US11460878B2

    公开(公告)日：2022-10-04

    申请号：US17375054

    申请日：2021-07-14

    Applicant: Kioxia Corporation

    Inventor： Toshitada Saito ,  Akihisa Fujimoto

    IPC: H03L7/07 ,  G06F1/06 ,  H04L7/00 ,  H04L7/033 ,  H03L7/091 ,  H03L7/00 ,  H04L25/08 ,  H04L25/14 ,  G06F1/12 ,  G06F13/38 ,  G06F13/42 ,  H03L7/08 ,  H03L7/099

    Abstract: According to one embodiment, an interface system includes a receiver, a first clock generator, a second clock generator, and a sampling circuit. The receiver is configured to receive a first clock and serial data from a host. The first clock generator includes a first voltage controlled oscillator (VCO) and is configured to generate a second clock on the basis of the first clock. The second clock generator includes a second voltage controlled oscillator (VCO) and is configured to generate a third clock on the basis of the serial data. The sampling circuit is configured to sample reception data on the basis of the third clock and the serial data.

    Interface system
    9.
    发明授权
    Interface system 有权

    公开(公告)号：US12228960B2

    公开(公告)日：2025-02-18

    申请号：US18601440

    申请日：2024-03-11

    Applicant: KIOXIA CORPORATION

    Inventor： Toshitada Saito ,  Akihisa Fujimoto

    IPC: G06F1/06 ,  G06F1/12 ,  G06F13/38 ,  G06F13/42 ,  H03L7/00 ,  H03L7/07 ,  H03L7/08 ,  H03L7/091 ,  H03L7/099 ,  H04L7/00 ,  H04L7/033 ,  H04L25/08 ,  H04L25/14

    Abstract: According to one embodiment, an interface system includes a receiver, a first clock generator, a second clock generator, and a sampling circuit. The receiver is configured to receive a first clock and serial data from a host. The first clock generator includes a first voltage controlled oscillator (VCO) and is configured to generate a second clock on the basis of the first clock. The second clock generator includes a second voltage controlled oscillator (VCO) and is configured to generate a third clock on the basis of the serial data. The sampling circuit is configured to sample reception data on the basis of the third clock and the serial data.

    Semiconductor device
    10.
    再颁专利
    Semiconductor device 有权

    公开(公告)号：USRE49424E1

    公开(公告)日：2023-02-21

    申请号：US17199945

    申请日：2021-03-12

    Applicant: Kioxia Corporation

    Inventor： Akihisa Fujimoto

    IPC: G06F3/00 ,  G06F12/06 ,  G06F13/42

    Abstract: According to one embodiment, a semiconductor device includes a device. The device includes a decoder, a generation circuit, a register, and a modifier. The decoder analyzes a command of a received packet. The generation circuit generates a unique device number in accordance with information in the packet. The register holds the generated unique device number. The modifier updates and outputs the packet. When a packet issued by a host is a command packet, among broadcast packets which return to the host through one or more devices, for determining the unique device number, the command packet includes parameters of an initial value and final value of device number.

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