公开(公告)号：US12232335B2

公开(公告)日：2025-02-18

申请号：US17890837

申请日：2022-08-18

Applicant: Hefei Reliance Memory Limited

Inventor： Zhichao Lu ,  Brent Steven Haukness

IPC: H10N70/20 ,  G11C7/12 ,  G11C13/00 ,  H10B63/00 ,  H10N70/00

Abstract: Disclosed is a resistive random access memory (RRAM). The RRAM includes a bottom electrode made of tungsten and a switching layer made of hafnium oxide disposed above the bottom electrode, wherein the switching layer includes a switchable filament. The RRAM further includes a resistive layer disposed above the switching layer and a bit line disposed above the resistive layer, wherein the resistive layer extends laterally to connect two or more memory cells along the bit line.

公开(公告)号：US11984163B2

公开(公告)日：2024-05-14

申请号：US17665123

申请日：2022-02-04

Applicant: HEFEI RELIANCE MEMORY LIMITED

Inventor： Deepak Chandra Sekar ,  Gary Bela Bronner ,  Frederick A. Ware

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0097 ,  G11C2213/15 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/75 ,  G11C2213/78 ,  G11C2213/79

Abstract: A memory cell includes a first resistive memory element, a second resistive memory element electrically coupled with the first resistive memory element at a common node, and a switching element comprising an input terminal electrically coupled with the common node, the switching element comprising a driver configured to float during one or more operations.

公开(公告)号：US11967374B2

公开(公告)日：2024-04-23

申请号：US17945676

申请日：2022-09-15

Applicant: HEFEI RELIANCE MEMORY LIMITED

Inventor： Danut Manea

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/0026 ,  G11C13/003 ,  G11C13/0038 ,  G11C13/004 ,  G11C2213/79

Abstract: Circuits and methods are disclosed for voltage-mode bit line precharge for random-access memory cells. A circuit includes an array of random access memory cells; a low-impedance voltage source configured to provide a precharge voltage; and a control circuit configured to precharge a bit line of one of the random access memory cells to the precharge voltage using the low-impedance voltage source prior to reading the one of the random access memory cells.

公开(公告)号：US20240105247A1

公开(公告)日：2024-03-28

申请号：US18528311

申请日：2023-12-04

Applicant: HEFEI RELIANCE MEMORY LIMITED

Inventor： Zhichao LU ,  Liang ZHAO

IPC: G11C11/22 ,  G06N3/06 ,  G06N5/04 ,  G11C11/4074 ,  G11C11/56

CPC classification number: G11C11/2273 ,  G06N3/06 ,  G06N5/04 ,  G11C11/2255 ,  G11C11/2257 ,  G11C11/4074 ,  G11C11/5642

Abstract: Dual-precision analog memory cells and arrays are provided. In some embodiments, a memory cell, comprises a non-volatile memory element having an input terminal and at least one output terminal; and a volatile memory element having a plurality of input terminals and an output terminal, wherein the output terminal of the volatile memory element is coupled to the input terminal of the non-volatile memory element, and wherein the volatile memory element comprises: a first transistor coupled between a first supply and a common node, and a second transistor coupled between a second supply and the common node; wherein the common node is coupled to the output terminal of the volatile memory element; and wherein gates of the first and second transistors are coupled to respective ones of the plurality of input terminals of the volatile memory element.

公开(公告)号：US11765914B2

公开(公告)日：2023-09-19

申请号：US17687900

申请日：2022-03-07

Applicant: HEFEI RELIANCE MEMORY LIMITED

Inventor： Jian Wu ,  Rene Meyer

IPC: H10B63/00 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10B63/80 ,  H10B63/22 ,  H10B63/84 ,  H10N70/023 ,  H10N70/043 ,  H10N70/24 ,  H10N70/245 ,  H10N70/801 ,  H10N70/826 ,  H10N70/828 ,  H10N70/841 ,  H10N70/8833 ,  H10N70/8836

Abstract: A memory cell including a two-terminal re-writeable non-volatile memory element having at least two layers of conductive metal oxide (CMO), which, in turn, can include a first layer of CMO including mobile oxygen ions, and a second layer of CMO formed in contact with the first layer of CMO to cooperate with the first layer of CMO to form an ion obstruction barrier. The ion obstruction barrier is configured to inhibit transport or diffusion of a subset of mobile ion to enhance, among other things, memory effects and cycling endurance of memory cells. At least one layer of an insulating metal oxide that is an electrolyte to the mobile oxygen ions and configured as a tunnel barrier is formed in contact with the second layer of CMO.

公开(公告)号：US11694744B2

公开(公告)日：2023-07-04

申请号：US17368182

申请日：2021-07-06

Applicant: HEFEI RELIANCE MEMORY LIMITED

Inventor： Liang Zhao ,  Zhichao Lu

IPC: G11C7/00 ,  G11C11/4094 ,  G11C11/408 ,  G11C11/4091 ,  G11C5/06 ,  G06F21/60 ,  G11C5/05

CPC classification number: G11C11/4094 ,  G06F21/602 ,  G11C5/05 ,  G11C5/06 ,  G11C11/4085 ,  G11C11/4091 ,  G06F2221/0755

Abstract: A non-volatile memory device includes a plurality of memory cells arranged in a matrix, a plurality of word lines extended in a row direction, and a plurality of bit lines extended in a column direction. Each of the memory cells is coupled to one of the word lines and one of the bit lines. The memory device further includes a word-line control circuit coupled to and configured to control the word lines, a first bit-line control circuit configured to control the bit lines and sense the memory cells in a digital mode, and a second bit-line control circuit configured to bias the bit lines and sense the memory cells in an analog mode. The first bit-line control circuit is coupled to a first end of each of the bit lines. The second bit-line control circuit is coupled to a second end of each of the bit lines.

公开(公告)号：US11551739B2

公开(公告)日：2023-01-10

申请号：US17308675

申请日：2021-05-05

Applicant: HEFEI RELIANCE MEMORY LIMITED

Inventor： Zhichao Lu ,  Liang Zhao

IPC: G11C7/00 ,  G11C11/22 ,  G06N5/04 ,  G11C11/56 ,  G06N3/06 ,  G11C11/4074

Abstract: Dual-precision analog memory cells and arrays are provided. In some embodiments, a memory cell, comprises a non-volatile memory element having an input terminal and at least one output terminal; and a volatile memory element having a plurality of input terminals and an output terminal, wherein the output terminal of the volatile memory element is coupled to the input terminal of the non-volatile memory element, and wherein the volatile memory element comprises: a first transistor coupled between a first supply and a common node, and a second transistor coupled between a second supply and the common node; wherein the common node is coupled to the output terminal of the volatile memory element; and wherein gates of the first and second transistors are coupled to respective ones of the plurality of input terminals of the volatile memory element.

公开(公告)号：US11489116B2

公开(公告)日：2022-11-01

申请号：US16789955

申请日：2020-02-13

Applicant: HEFEI RELIANCE MEMORY LIMITED

Inventor： Liang Zhao ,  Zhichao Lu

IPC: H01L45/00 ,  H01L27/24

Abstract: Thermal field controlled electrical conductivity change devices and applications therefore are provided. In some embodiments, a thermal switch, comprises: a metal-insulator-transition (MIT) material; first and second terminals electrically coupled to the MIT material; and a heater disposed near the MIT material.

公开(公告)号：US11468947B2

公开(公告)日：2022-10-11

申请号：US17128707

申请日：2020-12-21

Applicant: Hefei Reliance Memory Limited

Inventor： Zhichao Lu ,  Brent Haukness ,  Gary Bronner

IPC: G11C29/12 ,  G11C13/00

Abstract: The embodiments herein describe technologies of initializing resistive memory devices (e.g., non-volatile and volatile memory devices). In one method, a first voltage is applied across a resistance change material of a memory cell to form an initial filament and multiple cycles are performed to condition the initial filament. Each of the multiple cycles includes: applying a second voltage with a first polarity across the resistance change material; and applying a third voltage with a second polarity across the resistance change material.

公开(公告)号：US11373704B2

公开(公告)日：2022-06-28

申请号：US16890933

申请日：2020-06-02

Applicant: HEFEI RELIANCE MEMORY LIMITED

Inventor： Brent Steven Haukness

IPC: G11C13/00

Abstract: A resistive RAM (RRAM) device has a bit line, a word line, a source line carrying a bias voltage that is a substantially static and non-negative voltage, an RRAM cell, and a bit line control coupled to the bit line circuit. The RRAM cell includes a gate node coupled to the word line, a bias node coupled to the source line, and a bit line node coupled to the bit line. The bit line control circuit is configured to generate non-negative command voltages to perform respective memory operations on the RRAM cell.