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    Memory architecture and addressing for optimized density in integrated circuit package or on circuit board
    3.
    发明授权
    Memory architecture and addressing for optimized density in integrated circuit package or on circuit board 有权
    存储器结构和寻址，用于集成电路封装或电路板上的优化密度

    公开(公告)号：US06496400B2

    公开(公告)日：2002-12-17

    申请号：US09776447

    申请日：2001-02-02

    申请人： Christophe J. Chevallier

    发明人： Christophe J. Chevallier

    IPC分类号： G11C505

    CPC分类号： G11C8/12 ,  G11C5/05

    摘要： An electrically erasable and programmable read only memory (EEPROM) or other memory integrated circuit (IC) includes memory cells arranged in N blocks. The number of blocks, N, is selected to maximize utilization of the space available in a standard IC package. The number of blocks need not be an even power of two. More than log2(N) address bits are used to select between the blocks. A plurality of such memory ICs forms an array addressed by a memory controller, providing a number of directly addressable memory locations that need not be an even power of two. Addressing is provided for decoding chip select lines, block select lines, and other address lines. Staggered block decode lines associated with the memory blocks allow juxtaposition of the blocks to form a row in which connections are easily verified.

    摘要翻译： 电可擦除可编程只读存储器（EEPROM）或其他存储器集成电路（IC）包括以N个块排列的存储单元。 选择块数N，以最大限度地利用标准IC封装中可用的空间。 块的数量不需要是两个均匀的幂。 大于log2（N）的地址位用于在块之间进行选择。 多个这样的存储器IC形成由存储器控制器寻址的阵列，提供不需要是两个均匀功率的可直接寻址的存储器位置的数量。 提供寻址用于解码芯片选择线，块选择线和其他地址线。 与存储器块相关联的交错块解码线允许块的并置以形成容易验证连接的行。

    Reversible fixture for positioning magnetic memory cores
    4.
    发明授权
    Reversible fixture for positioning magnetic memory cores 失效
    用于定位磁记忆体的可逆固定

    公开(公告)号：US3698057A

    公开(公告)日：1972-10-17

    申请号：US3698057D

    申请日：1971-06-10

    申请人： RCA CORP

    发明人： WARNER CLIFFORD GEORGE ,  KADE JAMES HENRY

    IPC分类号： G11C5/05 ,  H05K13/04

    CPC分类号： G11C5/05 ,  Y10S29/044 ,  Y10S269/903 ,  Y10T29/53165

    摘要： A fixture for accurately positioning magnetic memory cores in an array has a top surface for receiving agitated magnetic cores and has a bottom surface for connection to a source of vacuum. The fixture comprises a flat rigid laminar metallic plate formed from a plurality of thin flexible sheets, having etched apertures, arranged in top, middle, and bottom groups, all bonded together in precise registry. The sheets of the top group and the sheets of the bottom group are the same in having rectangular apertures each dimensioned to receive a core edgewise to a depth of up to one-half of the outer diameter of the core. The sheets of the middle group have smaller apertures. The useful life of the fixture can be doubled by turning it over when the top surface becomes worn by the abrasive cores.

    摘要翻译： 用于将阵列中的磁记忆体芯精确地定位的固定装置具有用于接收搅动的磁芯的顶表面，并且具有用于连接到真空源的底表面。 夹具包括由多个薄柔性片形成的平坦的刚性层状金属板，其具有设置在顶部，中部和底部组中的蚀刻孔，所有这些都被精确地配准在一起。 顶部组的片材和底部片材的片材具有相同的矩形孔，其每个尺寸被设计成沿着芯的边缘的长度方向容纳至芯的外径的一半的深度。 中间组的片材具有较小的孔径。 当上表面被研磨芯磨损时，夹具的使用寿命可以翻一番。

    Method of manufacturing memory matrices
    5.
    发明授权
    Method of manufacturing memory matrices 失效
    制造存储器矩阵的方法

    公开(公告)号：US3587067A

    公开(公告)日：1971-06-22

    申请号：US3587067D

    申请日：1968-07-17

    申请人： PHILIPS CORP

    发明人： ENZ ULRICH ERNST

    IPC分类号： G11C5/05 ,  G11C5/08 ,  G11C5/04 ,  G11C11/06

    CPC分类号： G11C5/05 ,  G11C5/08 ,  Y10T29/49069

    摘要： A novel memory matrix and method of making same employing a support plate having formed therein recesses for receiving annular cores. The recesses include a group of conductive bars extending in each recess and above the plate surface. A group of circumscribing recesses are then provided, of a depth exceeding the core recesses but less than the plate thickness. Cores are then inserted into the recesses, and all recesses filled with an epoxy resin, up to slightly above the surface of the plate. The insulating surface is then printed with conductors interconnecting the ends of the bars as desired. The remaining metal on the other side of the support plate is then removed so that the circumscribed areas are electrically separated.