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    Phase Change Switch Arrangement
    1.
    发明公开
    Phase Change Switch Arrangement 审中-公开

    公开(公告)号：US20240122081A1

    公开(公告)日：2024-04-11

    申请号：US17961795

    申请日：2022-10-07

    Applicant: Infineon Technologies AG

    Inventor： Valentyn Solomko ,  Semen Syroiezhin ,  Dominik Heiss ,  Christian Butschkow ,  Jochen Braumueller

    IPC: H01L45/00

    CPC classification number: H01L45/06 ,  H01L45/1286 ,  H01L45/1226

    Abstract: A phase change switching device includes a substrate comprising a main surface, an RF input pad and a plurality of RF output pads disposed over the main surface, and phase change switch connections between the RF input pad and each of the RF output pads, wherein the phase change switch connections each include a phase change material and a heating element thermally coupled to the phase change material, wherein each of the RF output pads are arranged outside of an outer perimeter of the RF input pad, and wherein plurality of RF output pads at least partially surrounds the outer perimeter of the RF input pad.

    Phase Change Switch Fabricated with Front End of the Line Process
    2.
    发明公开
    Phase Change Switch Fabricated with Front End of the Line Process 审中-公开

    公开(公告)号：US20230389451A1

    公开(公告)日：2023-11-30

    申请号：US17826355

    申请日：2022-05-27

    Applicant: Infineon Technologies AG

    Inventor： Dominik Heiss ,  Matthias Markert

    IPC: H01L45/00

    CPC classification number: H01L45/1226 ,  H01L45/06 ,  H01L45/1286 ,  H01L45/1683

    Abstract: A method includes providing a semiconductor substrate comprising a main surface, forming a dielectric region on the main surface, forming a recess in the dielectric region, forming a strip of phase change material within the recess, forming a heating element that is thermally coupled to the strip of phase change material, forming an interconnection region over the main surface before or after forming the recess, the interconnection region including a metallization layer and a dielectric layer, electrically connecting the strip of phase change material to a connecting one of the metallization layers from the interconnection region, and completing formation of the interconnection region after electrically connecting the strip of phase change material, wherein completing formation of the interconnection region includes forming an outer one of the dielectric layers from the interconnection region that is disposed over the connecting one of the metallization layers and comprises a planar upper surface.

    PHASE CHANGE MEMORY GAPS
    4.
    发明公开
    PHASE CHANGE MEMORY GAPS 审中-公开

    公开(公告)号：US20230157185A1

    公开(公告)日：2023-05-18

    申请号：US17528197

    申请日：2021-11-17

    Applicant: International Business Machines Corporation

    Inventor： Injo Ok ,  Soon-Cheon Seo ,  Alexander Reznicek ,  Oleg Gluschenkov

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/06 ,  H01L27/24 ,  H01L45/1286 ,  H01L45/1253 ,  H01L45/1608

    Abstract: A PCM cell includes a first electrode, a heater/PCM portion electrically connected to first electrode, the heater/PCM portion comprising a PCM material, a second electrode electrically connected to the PCM material, and an electrical insulator stack surrounding the projection liner. The stack includes a plurality of first layers comprised of a first material and having a plurality of first inner sides facing towards the projection liner, and a plurality of second layers alternating with the plurality of first layers, the plurality of second layers comprised of a second material that is different from the first material, and the second plurality of layers having a plurality of second inner sides facing towards the projection liner. The plurality of second inner sides that are offset from the plurality of first inner sides forming a plurality of gaps.

    THERMAL MANAGEMENT OF SELECTOR
    5.
    发明申请
    THERMAL MANAGEMENT OF SELECTOR 审中-公开

    公开(公告)号：US20180158870A1

    公开(公告)日：2018-06-07

    申请号：US15874977

    申请日：2018-01-19

    Applicant: Western Digital Technologies, Inc.

    Inventor： Mac D. APODACA ,  Kurt Allan RUBIN

    IPC: H01L27/24 ,  H01L45/00

    CPC classification number: H01L27/2409 ,  H01L27/2427 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1286 ,  H01L45/141 ,  H01L45/144

    Abstract: A non-volatile memory device that limits the temperature excursion of a selector during operation to enhance the cycling life of the non-volatile memory device. A selector, in line with a memory element, may be degraded with repeated temperature excursions as current passes through a stack during the read/write process. The selector changes from an amorphous state to become crystalline thus reducing the life of a memory device. The memory device includes a word line, a bit line disposed perpendicular to the word line, a stack—including a memory element, a selector, and a spacer—disposed between the word line and bit line, and one or more insulating layers surrounding an outer surface of the stack disposed between the word line and bit line. By surrounding the selector with a high thermal conductive heat-sink material, heat is directed away from the selector helping maintain the selector's amorphous state longer.

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