公开(公告)号：US20240074210A1

公开(公告)日：2024-02-29

申请号：US18164926

申请日：2023-02-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiyeon YANG ,  Bonwon Koo ,  Hajun Sung ,  Changseung Lee ,  Minwoo Choi

IPC: H10B63/00 ,  H10N70/00

CPC classification number: H10B63/24 ,  H10B63/84 ,  H10N70/841 ,  H10N70/8828

Abstract: Disclosed are a memory device and a memory apparatus including the memory device. The memory device may include a first electrode, a second electrode spaced apart from the first electrode, an intermediate layer between the first electrode and the second electrode, and an interface layer in contact with the intermediate layer. The intermediate layer and the interface layer each may have ovonic threshold switching (OTS) characteristics. A material of the interface layer may have a threshold voltage shift greater than a threshold voltage shift (A Vth) of the intermediate layer.

公开(公告)号：US20240107778A1

公开(公告)日：2024-03-28

申请号：US18298642

申请日：2023-04-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changseung LEE ,  Kiyeon Yang ,  Youngjae Kang ,  Hajun Sung ,  Dongho Ahn

IPC: H10B63/10 ,  H10B63/00

CPC classification number: H10B63/10 ,  H10B63/24 ,  H10B63/80

Abstract: A phase-change memory structure includes lower and upper electrodes spaced apart from each other, and a phase-change material stack between the lower and upper electrodes. The phase-change material stack includes a plurality of phase-change layers, at least two phase-change layers of the plurality of phase-change layers have different phase-change temperatures, and a plurality of barrier layers between the plurality of phase-change layers The at least two phase-change layers of the plurality of phase-change layers have different thicknesses.

公开(公告)号：US12254922B2

公开(公告)日：2025-03-18

申请号：US18157408

申请日：2023-01-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minwoo Choi ,  Young Jae Kang ,  Bonwon Koo ,  Yongyoung Park ,  Hajun Sung ,  Dongho Ahn ,  Kiyeon Yang ,  Wooyoung Yang ,  Changseung Lee

IPC: G11C13/00 ,  H10B63/10 ,  H10B63/00

Abstract: A memory device includes a memory cell including a selection layer and a phase change material layer, and a controller, wherein the selection layer includes a switching material, the phase change material layer includes a phase change material, and the controller is configured to apply a write pulse to the selection layer and the phase change material layer and control a polarity, a peak value, and a shape of the write pulse.

公开(公告)号：US12101942B2

公开(公告)日：2024-09-24

申请号：US18478776

申请日：2023-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wooyoung Yang ,  Bonwon Koo ,  Chungman Kim ,  Kwangmin Park ,  Hajun Sung ,  Dongho Ahn ,  Changseung Lee ,  Minwoo Choi

IPC: H10B63/00 ,  G11C13/00 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10B63/24 ,  G11C13/0004 ,  H10B61/10 ,  H10B63/84 ,  H10N50/01 ,  H10N50/80 ,  H10N70/063 ,  H10N70/231 ,  H10N70/24 ,  H10N70/25 ,  H10N70/8413 ,  H10N70/8825 ,  H10N70/8828 ,  H10N70/8833 ,  H10N70/8836

Abstract: A chalcogen compound layer exhibiting ovonic threshold switching characteristics, a switching device, a semiconductor device, and/or a semiconductor apparatus including the same are provided. The switching device and/or the semiconductor device may include two or more chalcogen compound layers having different energy band gaps. Alternatively, the switching device and/or semiconductor device may include a chalcogen compound layer having a concentration gradient of an element of boron (B), aluminum (Al), scandium (Sc), manganese (Mn), strontium (Sr), and/or indium (In) in a thickness direction thereof. The switching device and/or a semiconductor device may exhibit stable switching characteristics while having a low off-current value (leakage current value).

公开(公告)号：US20240057347A1

公开(公告)日：2024-02-15

申请号：US18348846

申请日：2023-07-07

Applicant: Samsung Electronics Co., Ltd. ,  UIF (University Industry Foundation), Yonsei University

Inventor： Wooyoung YANG ,  Hyungjun Kim ,  Hajun Sung ,  Kiyeon Yang ,  Changseung Lee ,  Changyup Park ,  Seung-min Chung ,  Sangyoon Lee ,  Inkyu Sohn

IPC: H10B63/10 ,  H10N70/20 ,  H10N70/00 ,  H10B63/00

CPC classification number: H10B63/10 ,  H10N70/231 ,  H10N70/8822 ,  H10N70/826 ,  H10N70/828 ,  H10B63/20 ,  H10N70/023 ,  H10N70/8825

Abstract: A memory element includes a substrate, a first electrode formed on the substrate, a phase-change heterolayer formed on the first electrode and electrically connected to the first electrode, and a second electrode formed on the phase-change heterolayer, wherein the phase-change heterolayer includes one or more confinement material layers and one or more phase-change material layers, and the confinement material layer includes a metal chalcogenide film.

公开(公告)号：US20240046986A1

公开(公告)日：2024-02-08

申请号：US18157408

申请日：2023-01-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minwoo CHOI ,  Young Jae Kang ,  Bonwon Koo ,  Yongyoung Park ,  Hajun Sung ,  Dongho Ahn ,  Kiyeon Yang ,  Wooyoung Yang ,  Changseung Lee

IPC: G11C13/00 ,  H10B63/10

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  H10B63/10 ,  G11C2213/30 ,  H10B63/84

Abstract: A memory device includes a memory cell including a selection layer and a phase change material layer, and a controller, wherein the selection layer includes a switching material, the phase change material layer includes a phase change material, and the controller is configured to apply a write pulse to the selection layer and the phase change material layer and control a polarity, a peak value, and a shape of the write pulse.

公开(公告)号：US11818899B2

公开(公告)日：2023-11-14

申请号：US17244212

申请日：2021-04-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wooyoung Yang ,  Bonwon Koo ,  Chungman Kim ,  Kwangmin Park ,  Hajun Sung ,  Dongho Ahn ,  Changseung Lee ,  Minwoo Choi

IPC: H10B63/00 ,  G11C13/00 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H10N70/20 ,  H10N70/00

CPC classification number: H10B63/24 ,  G11C13/0004 ,  H10B61/10 ,  H10B63/84 ,  H10N50/01 ,  H10N50/80 ,  H10N70/063 ,  H10N70/231 ,  H10N70/24 ,  H10N70/25 ,  H10N70/8413 ,  H10N70/8825 ,  H10N70/8828 ,  H10N70/8833 ,  H10N70/8836

Abstract: A chalcogen compound layer exhibiting ovonic threshold switching characteristics, a switching device, a semiconductor device, and/or a semiconductor apparatus including the same are provided. The switching device and/or the semiconductor device may include two or more chalcogen compound layers having different energy band gaps. Alternatively, the switching device and/or semiconductor device may include a chalcogen compound layer having a concentration gradient of an element of boron (B), aluminum (Al), scandium (Sc), manganese (Mn), strontium (Sr), and/or indium (In) in a thickness direction thereof. The switching device and/or a semiconductor device may exhibit stable switching characteristics while having a low off-current value (leakage current value).