-
公开(公告)号：US20240074210A1
公开(公告)日：2024-02-29
申请号：US18164926
申请日：2023-02-06
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kiyeon YANG , Bonwon Koo , Hajun Sung , Changseung Lee , Minwoo Choi
CPC classification number: H10B63/24 , H10B63/84 , H10N70/841 , H10N70/8828
Abstract: Disclosed are a memory device and a memory apparatus including the memory device. The memory device may include a first electrode, a second electrode spaced apart from the first electrode, an intermediate layer between the first electrode and the second electrode, and an interface layer in contact with the intermediate layer. The intermediate layer and the interface layer each may have ovonic threshold switching (OTS) characteristics. A material of the interface layer may have a threshold voltage shift greater than a threshold voltage shift (A Vth) of the intermediate layer.
-
Patent Agency Ranking
公开(公告)号：US12254922B2
公开(公告)日：2025-03-18
申请号：US18157408
申请日：2023-01-20
Applicant: Samsung Electronics Co., Ltd.
Inventor： Minwoo Choi , Young Jae Kang , Bonwon Koo , Yongyoung Park , Hajun Sung , Dongho Ahn , Kiyeon Yang , Wooyoung Yang , Changseung Lee
Abstract: A memory device includes a memory cell including a selection layer and a phase change material layer, and a controller, wherein the selection layer includes a switching material, the phase change material layer includes a phase change material, and the controller is configured to apply a write pulse to the selection layer and the phase change material layer and control a polarity, a peak value, and a shape of the write pulse.
-
公开(公告)号：US20240065118A1
公开(公告)日：2024-02-22
申请号：US18068821
申请日：2022-12-20
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hajun SUNG , Youngjae Kang , Changyup Park , Kiyeon Yang , Wooyoung Yang , Changseung Lee , Minwoo Choi
CPC classification number: H10N70/231 , H10N70/861 , H10N70/8828 , H10N70/8845 , H10B63/84
Abstract: Provided are a phase change heterostructure and a phase change memory device including the same. The phase change memory device including the phase change heterostructure may include a plurality of memory cells. Each of the plurality of memory cells may include a first electrode and a second electrode, which may be spaced apart from each other, and a phase change heterostructure between the first electrode and the second electrode. The phase change heterostructure may include a plurality of phase change material layers and a plurality of thermal barrier layers alternately stacked on each other. A material of the plurality of thermal barrier layers have a thermal conductivity lower than a materials of the plurality of phase change material layers.
-
4.发明授权公开(公告)号：US12101942B2
公开(公告)日：2024-09-24
申请号：US18478776
申请日：2023-09-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Wooyoung Yang , Bonwon Koo , Chungman Kim , Kwangmin Park , Hajun Sung , Dongho Ahn , Changseung Lee , Minwoo Choi
CPC classification number: H10B63/24 , G11C13/0004 , H10B61/10 , H10B63/84 , H10N50/01 , H10N50/80 , H10N70/063 , H10N70/231 , H10N70/24 , H10N70/25 , H10N70/8413 , H10N70/8825 , H10N70/8828 , H10N70/8833 , H10N70/8836
Abstract: A chalcogen compound layer exhibiting ovonic threshold switching characteristics, a switching device, a semiconductor device, and/or a semiconductor apparatus including the same are provided. The switching device and/or the semiconductor device may include two or more chalcogen compound layers having different energy band gaps. Alternatively, the switching device and/or semiconductor device may include a chalcogen compound layer having a concentration gradient of an element of boron (B), aluminum (Al), scandium (Sc), manganese (Mn), strontium (Sr), and/or indium (In) in a thickness direction thereof. The switching device and/or a semiconductor device may exhibit stable switching characteristics while having a low off-current value (leakage current value).
-
公开(公告)号：US11818899B2
公开(公告)日：2023-11-14
申请号：US17244212
申请日：2021-04-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Wooyoung Yang , Bonwon Koo , Chungman Kim , Kwangmin Park , Hajun Sung , Dongho Ahn , Changseung Lee , Minwoo Choi
CPC classification number: H10B63/24 , G11C13/0004 , H10B61/10 , H10B63/84 , H10N50/01 , H10N50/80 , H10N70/063 , H10N70/231 , H10N70/24 , H10N70/25 , H10N70/8413 , H10N70/8825 , H10N70/8828 , H10N70/8833 , H10N70/8836
Abstract: A chalcogen compound layer exhibiting ovonic threshold switching characteristics, a switching device, a semiconductor device, and/or a semiconductor apparatus including the same are provided. The switching device and/or the semiconductor device may include two or more chalcogen compound layers having different energy band gaps. Alternatively, the switching device and/or semiconductor device may include a chalcogen compound layer having a concentration gradient of an element of boron (B), aluminum (Al), scandium (Sc), manganese (Mn), strontium (Sr), and/or indium (In) in a thickness direction thereof. The switching device and/or a semiconductor device may exhibit stable switching characteristics while having a low off-current value (leakage current value).
-
6.发明公开公开(公告)号：US20230329007A1
公开(公告)日：2023-10-12
申请号：US18176750
申请日：2023-03-01
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hajun SUNG , Youngjae Kang , Bonwon Koo , Yongyoung Park , Dongho Ahn , Kiyeon Yang , Wooyoung Yang , Changseung Lee , Minwoo Choi
Abstract: A chalcogenide material according to one embodiment includes germanium (Ge); arsenic (As); sulfur (S); selenium (Se), and at least one group III metal selected from indium (In), gallium (Ga), and aluminum (Al), wherein the content of the Ge may be greater than about 10 at % and less than or equal to about 30 at %, the content of the As may be greater than about 30 at % and less than or equal to about 50 at %, the content of Se is greater than about 20 at % and less than or equal to about 60 at %, the content of S is greater than about 0.5 at % and less than or equal to about 10 at %, and the content of the group III metal may be in the range of 0.5 at % to 10 at %.
-
-
-
-
-
Search Results
6
records
(took 0.014 seconds)
