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公开(公告)号：US11963368B2
公开(公告)日：2024-04-16
申请号：US17330295
申请日：2021-05-25
发明人： Chun-Chieh Mo , Shih-Chi Kuo , Tsai-Hao Hung
IPC分类号： H10B63/00 , H10B61/00 , H10N50/01 , H10N50/10 , H10N50/80 , H10N50/85 , H10N70/00 , H10N70/20
CPC分类号： H10B63/24 , H10B61/10 , H10B63/80 , H10N50/01 , H10N50/10 , H10N50/80 , H10N70/021 , H10N70/063 , H10N70/231 , H10N70/24 , H10N70/245 , H10N70/826 , H10N70/841 , H10N50/85 , H10N70/8825 , H10N70/8833 , H10N70/8845
摘要： A memory includes: a dielectric fin formed over a substrate; and a pair of memory cells disposed along respective sidewalls of the dielectric fin, each of the pair of memory cells comprising: a first conductor layer; a selector layer; a resistive material layer; and a second conductor layer, wherein the first conductor layer, selector layer, resistive material layer, and second conductor layer each includes upper and lower boundaries, and at least one of the upper and lower boundaries is tilted away from one of the sidewalls of the dielectric fin by an angle.
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公开(公告)号：US11923003B2
公开(公告)日：2024-03-05
申请号：US17583740
申请日：2022-01-25
申请人： Nantero, Inc.
发明人： Jia Luo , Lee E. Cleveland , Ton Yan Tony Chan
IPC分类号： G11C11/00 , G11C11/56 , G11C13/00 , G11C13/02 , H10B63/00 , H10K10/50 , H10K19/00 , H10K85/20 , H10N70/00
CPC分类号： G11C11/5664 , G11C13/0014 , G11C13/003 , G11C13/0069 , G11C13/025 , H10B63/84 , H10K10/50 , H10K19/202 , H10K85/211 , H10K85/221 , H10N70/841 , H10N70/8845 , G11C13/0004 , G11C13/0007 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C2213/35 , G11C2213/79
摘要： Combinations of resistive change elements and resistive change element arrays thereof are described. Combinational resistive change elements and combinational resistive change element arrays thereof are described. Devices and methods for programming and accessing combinations of resistive change elements are described. Devices and methods for programming and accessing combinational resistive change elements are described.
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公开(公告)号：US11723292B2
公开(公告)日：2023-08-08
申请号：US16910609
申请日：2020-06-24
发明人： Chih-Yang Chang , Wen-Ting Chu , Kuo-Chi Tu , Yu-Wen Liao , Hsia-Wei Chen , Chin-Chieh Yang , Sheng-Hung Shih , Wen-Chun You
CPC分类号： H10N70/8265 , H10B63/30 , H10N70/011 , H10N70/063 , H10N70/066 , H10N70/20 , H10N70/24 , H10N70/826 , H10N70/841 , H10N70/8833 , H10N70/021 , H10N70/023 , H10N70/026 , H10N70/028 , H10N70/041 , H10N70/043 , H10N70/046 , H10N70/061 , H10N70/068 , H10N70/231 , H10N70/235 , H10N70/245 , H10N70/25 , H10N70/253 , H10N70/257 , H10N70/801 , H10N70/821 , H10N70/823 , H10N70/828 , H10N70/8413 , H10N70/8416 , H10N70/8418 , H10N70/8613 , H10N70/8616 , H10N70/881 , H10N70/882 , H10N70/883 , H10N70/884 , H10N70/8822 , H10N70/8825 , H10N70/8828 , H10N70/8836 , H10N70/8845
摘要： The present disclosure, in some embodiments, relates to a memory device. The memory device includes a dielectric protection layer having sidewalls defining an opening over a conductive interconnect within an inter-level dielectric (ILD) layer. A bottom electrode structure extends from within the opening to directly over the dielectric protection layer. A variable resistance layer is over the bottom electrode structure and a top electrode is over the variable resistance layer. A top electrode via is disposed on the top electrode and directly over the dielectric protection layer.
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4.发明公开公开(公告)号：US20240237566A1
公开(公告)日：2024-07-11
申请号：US18443283
申请日：2024-02-15
发明人： Jea Gun PARK , Dae Seong WOO , Soo Min JIN , Sang Hong PARK , Sung Mok JUNG
CPC分类号： H10N70/8845 , G06N3/063 , H10B63/80 , H10N70/026 , H10N70/24 , H10N70/841
摘要： Disclosed is an artificial synapse device including an amorphous carbon oxide-based resistance change memory device and a method of fabricating the same, and more particularly to a technology for providing an artificial synapse device capable of implementing the characteristics of biological synapses responsible for memory and information transfer in the human brain using a resistance change memory device. More particularly, the artificial synapse device according to an embodiment of the provided includes a first electrode; a second electrode disposed to face the first electrode; and a switching layer formed of an amorphous carbon oxide deposited by injecting oxygen when sputtering carbon into a target between the first electrode and the second electrode, wherein the artificial synapse device has synaptic characteristics wherein a value of an output current changes gradually when a same voltage of either set voltage or reset voltage is repeatedly applied to the first electrode.
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公开(公告)号：US20240065118A1
公开(公告)日：2024-02-22
申请号：US18068821
申请日：2022-12-20
发明人： Hajun SUNG , Youngjae Kang , Changyup Park , Kiyeon Yang , Wooyoung Yang , Changseung Lee , Minwoo Choi
CPC分类号： H10N70/231 , H10N70/861 , H10N70/8828 , H10N70/8845 , H10B63/84
摘要： Provided are a phase change heterostructure and a phase change memory device including the same. The phase change memory device including the phase change heterostructure may include a plurality of memory cells. Each of the plurality of memory cells may include a first electrode and a second electrode, which may be spaced apart from each other, and a phase change heterostructure between the first electrode and the second electrode. The phase change heterostructure may include a plurality of phase change material layers and a plurality of thermal barrier layers alternately stacked on each other. A material of the plurality of thermal barrier layers have a thermal conductivity lower than a materials of the plurality of phase change material layers.
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公开(公告)号：US11737290B2
公开(公告)日：2023-08-22
申请号：US17542638
申请日：2021-12-06
发明人： Chin-Chieh Yang , Chih-Yang Chang , Wen-Ting Chu , Yu-Wen Liao
IPC分类号： H10B63/00 , G11C13/00 , H10N70/20 , H10N70/00 , H01L23/522 , H01L23/528 , H01L27/10
CPC分类号： H10B63/82 , G11C13/0011 , G11C13/0069 , H10B63/30 , H10B63/80 , H10N70/063 , H10N70/20 , H10N70/24 , H10N70/826 , H10N70/841 , H10N70/8833 , H10N70/8836 , G11C13/004 , G11C13/0023 , G11C2213/79 , H01L23/5226 , H01L23/5283 , H01L27/101 , H10B63/84 , H10N70/011 , H10N70/023 , H10N70/821 , H10N70/8845
摘要： The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first resistive random access memory (RRAM) element over a substrate. The first RRAM element has a first terminal and a second terminal. A second RRAM element is arranged over the substrate and has a third terminal and a fourth terminal. The third terminal is electrically coupled to the first terminal of the first RRAM element. A reading circuit is coupled to the second terminal and the fourth terminal. The reading circuit is configured to read a single data state from both a first non-zero read current received from the first RRAM element and a second non-zero read current received from the second RRAM element.
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公开(公告)号：US12075634B2
公开(公告)日：2024-08-27
申请号：US18347794
申请日：2023-07-06
发明人： Chin-Chieh Yang , Chih-Yang Chang , Wen-Ting Chu , Yu-Wen Liao
IPC分类号： H10B63/00 , G11C13/00 , H10N70/00 , H10N70/20 , H01L23/522 , H01L23/528 , H01L27/10
CPC分类号： H10B63/82 , G11C13/0011 , G11C13/0069 , H10B63/30 , H10B63/80 , H10N70/063 , H10N70/20 , H10N70/24 , H10N70/826 , H10N70/841 , H10N70/8833 , H10N70/8836 , G11C13/0002 , G11C13/0023 , G11C13/004 , G11C2213/79 , H01L23/5226 , H01L23/5283 , H01L27/101 , H10B63/32 , H10B63/84 , H10N70/011 , H10N70/023 , H10N70/821 , H10N70/8845
摘要： The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first resistive random access memory (RRAM) element and a second RRAM element over a substrate. A conductive element is arranged below the first RRAM element and the second RRAM element. The conductive element electrically couples the first RRAM element to the second RRAM element. An upper insulating layer continuously extends over the first RRAM element and the second RRAM element. An upper inter-level dielectric (ILD) structure laterally surrounds the first RRAM element and the second RRAM element. The upper insulating layer separates the first RRAM element and the second RRAM element from the upper ILD structure.
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公开(公告)号：US20240260278A1
公开(公告)日：2024-08-01
申请号：US18632132
申请日：2024-04-10
发明人： Chun-Chieh MO , Shih-Chi KUO , Tsai-Hao HUNG
IPC分类号： H10B63/00 , H10B61/00 , H10N50/01 , H10N50/10 , H10N50/80 , H10N50/85 , H10N70/00 , H10N70/20
CPC分类号： H10B63/24 , H10B61/10 , H10B63/80 , H10N50/01 , H10N50/10 , H10N50/80 , H10N70/021 , H10N70/063 , H10N70/231 , H10N70/24 , H10N70/245 , H10N70/826 , H10N70/841 , H10N50/85 , H10N70/8825 , H10N70/8833 , H10N70/8845
摘要： A memory includes: a dielectric fin formed over a substrate; and a pair of memory cells disposed along respective sidewalls of the dielectric fin, each of the pair of memory cells comprising: a first conductor layer; a selector layer; a resistive material layer; and a second conductor layer, wherein the first conductor layer, selector layer, resistive material layer, and second conductor layer each includes upper and lower boundaries, and at least one of the upper and lower boundaries is tilted away from one of the sidewalls of the dielectric fin by an angle.
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9.发明授权公开(公告)号：US11910732B2
公开(公告)日：2024-02-20
申请号：US17750484
申请日：2022-05-23
CPC分类号： H10N70/231 , H10B63/24 , H10B63/84 , H10N70/021 , H10N70/8845
摘要： An array of rail structures is formed over a substrate. Each rail structure includes at least one bit line. Dielectric isolation structures straddling the array of rail structures are formed. Line trenches are provided between neighboring pairs of the dielectric isolation structures. A layer stack of a resistive memory material layer and a selector material layer is formed within each of the line trenches. A word line is formed on each of the layer stacks within unfilled volumes of the line trenches. The word lines or at least a subset of the bit lines includes a carbon-based conductive material containing hybridized carbon atoms in a hexagonal arrangement to provide a low resistivity conductive structure. An array of resistive memory elements is formed over the substrate. A plurality of arrays of resistive memory elements may be formed at different levels over the substrate.
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公开(公告)号：US11778933B2
公开(公告)日：2023-10-03
申请号：US17469080
申请日：2021-09-08
发明人： Charles Tolle , Haiping Hong , Christian Widener , Greg Christensen , Jack Yang
CPC分类号： H10N70/8845 , C10M103/02 , H10B63/20 , B82Y30/00 , C10N2020/00 , C10N2050/10
摘要： A non-volatile memory circuit in embodiments of the present invention may have one or more of the following features: (a) a logic source, and (b) a semi-conductive device being electrically coupled to the logic source, having a first terminal, a second terminal and a nano-grease with significantly reduced amount of carbon nanotube loading located between the first and second terminal, wherein the nano-grease exhibits non-volatile memory characteristics.
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