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    Resistance change device and storage device
    3.
    发明授权
    Resistance change device and storage device 有权

    公开(公告)号：US11917930B2

    公开(公告)日：2024-02-27

    申请号：US17462819

    申请日：2021-08-31

    申请人： Kioxia Corporation

    发明人： Takao Kosaka ,  Hiroki Tokuhira

    IPC分类号： H10N70/00 ,  H10B63/00 ,  H10N70/20 ,  G11C13/00

    CPC分类号： H10N70/8828 ,  H10B63/24 ,  H10B63/84 ,  H10N70/235 ,  H10N70/841 ,  H10N70/8822 ,  H10N70/8825 ,  G11C2013/008

    摘要： A resistance change device of an embodiment includes: a first electrode; a second electrode; and a stack disposed between these electrodes, and including a first layer containing a resistance change material and a second layer in contact with the first layer. The resistance change material contains at least one of a first element such as Ge and a second element such as Sb, and at least one third element selected from Te, Se, S, and O. The second layer contains a crystal material containing at least one selected from a group consisting of a first material having a composition represented by (Ti,Zr,Hf)CoSb, (Zr,Hf)NiSn, or Fe(Nb,Zr,Hf)(Sb,Sn), a second material having a composition represented by Fe(V,Hf,W)(Al,Si), and a third material having a composition represented by Mg(Si,Ge,Sn).

    CROSS-POINT MEMORY ARRAY WITH ACCESS LINES
    6.
    发明公开
    CROSS-POINT MEMORY ARRAY WITH ACCESS LINES 审中-公开

    公开(公告)号：US20240292632A1

    公开(公告)日：2024-08-29

    申请号：US18657259

    申请日：2024-05-07

    申请人： Micron Technology, Inc.

    发明人： Hernan A. Castro ,  Stephen H. Tang ,  Stephen W. Russell

    IPC分类号： H10B63/00 ,  H10B53/20 ,  H10N70/20

    CPC分类号： H10B63/845 ,  H10B53/20 ,  H10B63/20 ,  H10B63/22 ,  H10B63/24 ,  H10B63/80 ,  H10B63/84 ,  H10N70/235 ,  H10N70/245

    摘要： Methods and apparatuses for a cross-point memory array and related fabrication techniques are described. The fabrication techniques described herein may facilitate concurrently building two or more decks of memory cells disposed in a cross-point architecture. Each deck of memory cells may include a plurality of first access lines (e.g., word lines), a plurality of second access lines (e.g., bit lines), and a memory component at each topological intersection of a first access line and a second access line. The fabrication technique may use a pattern of vias formed at a top layer of a composite stack, which may facilitate building a 3D memory array within the composite stack while using a reduced number of processing steps. The fabrication techniques may also be suitable for forming a socket region where the 3D memory array may be coupled with other components of a memory device.

    Cross-point memory array with access lines
    10.
    发明授权
    Cross-point memory array with access lines 有权

    公开(公告)号：US12035543B2

    公开(公告)日：2024-07-09

    申请号：US17064099

    申请日：2020-10-06

    申请人： Micron Technology, Inc.

    发明人： Hernan A. Castro ,  Stephen H. Tang ,  Stephen W. Russell

    IPC分类号： H10B63/00 ,  H10B53/20 ,  H10N70/20

    CPC分类号： H10B63/845 ,  H10B53/20 ,  H10B63/20 ,  H10B63/22 ,  H10B63/24 ,  H10B63/80 ,  H10B63/84 ,  H10N70/235 ,  H10N70/245

    摘要： Methods and apparatuses for a cross-point memory array and related fabrication techniques are described. The fabrication techniques described herein may facilitate concurrently building two or more decks of memory cells disposed in a cross-point architecture. Each deck of memory cells may include a plurality of first access lines (e.g., word lines), a plurality of second access lines (e.g., bit lines), and a memory component at each topological intersection of a first access line and a second access line. The fabrication technique may use a pattern of vias formed at a top layer of a composite stack, which may facilitate building a 3D memory array within the composite stack while using a reduced number of processing steps. The fabrication techniques may also be suitable for forming a socket region where the 3D memory array may be coupled with other components of a memory device.