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公开(公告)号：US12026605B2
公开(公告)日：2024-07-02
申请号：US17110429
申请日：2020-12-03
CPC分类号： G06N3/063 , G06N3/08 , G11C11/223 , G11C11/2273 , G11C11/2275 , G11C11/54 , H10B51/30
摘要： A circuit structure includes a first ferroelectric field effect transistor (FeFET) having a first gate electrode, a first source electrode, and a first drain electrode and a second FeFET having a second gate electrode, a second source electrode, and a second drain electrode. The first gate electrode is connected to a wordline, and the first source electrode and the second source electrode are connected to a bitline. The first drain electrode is connected to the second gate electrode and the second drain electrode is connected to a bias line. A weight synapse structure is constructed by combining two circuit structures. A plurality of weight synapse structures are incorporated into a crossbar array.
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公开(公告)号：US11864474B2
公开(公告)日：2024-01-02
申请号：US17655184
申请日：2022-03-17
发明人： Takashi Ando , Franco Stellari , Guy M. Cohen , Nanbo Gong
CPC分类号： H10N70/257 , G11C13/004 , G11C29/50
摘要： A semiconductor device is provided. The semiconductor device includes a resistive memory device, and at least a first photodetector and a second photodetector positioned adjacent to the resistive memory device to allow for measurement of the intensity of photon emission from a filament of the resistive memory device.
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公开(公告)号：US11856798B2
公开(公告)日：2023-12-26
申请号：US17652970
申请日：2022-03-01
发明人： Guy M. Cohen , Takashi Ando , Nanbo Gong
CPC分类号： H10B63/80 , G11C13/0002 , H03K3/84 , H10N70/021 , H10N70/826 , H10N70/841
摘要： A random number generator comprising resistive random-access memory (RRAM) devices including: a first electrode; a second electrode; a third electrode located between the first and second electrode; at least one electrically insulating layer separating the first electrode and the second electrode from the third electrode, wherein the at least one electrically insulating layer has a substantially uniform thickness; a first filament that is current conducting and extends through the at least one electrically insulating layer; a second filament is located in the at least one electrically insulating layer and does not extend through the at least one electrically insulating layer; a voltage source configured to apply voltage to at least one of the first electrode and the second electrode; and a voltage sensor configured to sense voltage of the third electrode in order to determine which one of the first filament or the second filament is more resistive.
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公开(公告)号：US20230301212A1
公开(公告)日：2023-09-21
申请号：US17655184
申请日：2022-03-17
发明人： Takashi Ando , Franco Stellari , Guy M. Cohen , Nanbo Gong
CPC分类号： H01L45/1213 , G11C13/004 , G11C29/50
摘要： A semiconductor device is provided. The semiconductor device includes a resistive memory device, and at least a first photodetector and a second photodetector positioned adjacent to the resistive memory device to allow for measurement of the intensity of photon emission from a filament of the resistive memory device.
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公开(公告)号：US20230284462A1
公开(公告)日：2023-09-07
申请号：US17652970
申请日：2022-03-01
发明人： Guy M. Cohen , Takashi Ando , Nanbo Gong
CPC分类号： H01L27/2463 , H01L45/1253 , H01L45/1608 , G11C13/0002 , H03K3/84 , H01L45/1233
摘要： A random number generator comprising resistive random-access memory (RRAM) devices including: a first electrode; a second electrode; a third electrode located between the first and second electrode; at least one electrically insulating layer separating the first electrode and the second electrode from the third electrode, wherein the at least one electrically insulating layer has a substantially uniform thickness; a first filament that is current conducting and extends through the at least one electrically insulating layer; a second filament is located in the at least one electrically insulating layer and does not extend through the at least one electrically insulating layer; a voltage source configured to apply voltage to at least one of the first electrode and the second electrode; and a voltage sensor configured to sense voltage of the third electrode in order to determine which one of the first filament or the second filament is more resistive.
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公开(公告)号：US11302810B1
公开(公告)日：2022-04-12
申请号：US16953505
申请日：2020-11-20
发明人： Nanbo Gong , Takashi Ando , Guy M. Cohen
IPC分类号： H01L21/02 , H01L21/324 , H01L29/06 , H01L29/423 , H01L29/49 , H01L29/51 , H01L29/66 , H01L29/78 , H01L29/786
摘要： A ferroelectric field effect transistor (FeFET) is provided. The FeFET includes a buried oxide (BOX) layer; a nanowire layer including pads formed on the BOX layer at source and drain regions of the FeFET, and a nanowire core extending between the pads and over a recess formed in the BOX layer; a metal electrode coating the nanowire core; a ferroelectric layer coating the metal electrode; an interfacial layer coating the ferroelectric layer; and a polysilicon layer formed over a channel region of the FeFET, the polysilicon layer coating the interfacial layer.
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公开(公告)号：US20210375360A1
公开(公告)日：2021-12-02
申请号：US17404157
申请日：2021-08-17
发明人： Nanbo Gong , Wei-Chih Chien , Matthew Joseph BrightSky , Christopher P. Miller , Hsiang-Lan Lung
摘要： A multi-level cell (MLC) one-selector-one-resistor (1S1R) three-dimensional (3D) cross-point memory system includes at least one MLC 1S1R structure including a stacked arrangement of a phase change memory (PCM) cell and a threshold switch selector. An electrically conductive bit line is in electrical communication with the OTS selector, and an electrically conductive word line is in electrical communication with the PCM cell. A controller is in electrical communication with the bit line and the word line. The controller is configured to select at least one voltage pulse from a group of different voltage pulses comprising a read pulse, a partial set pulse, a set pulse, a partial reset pulse, and a reset pulse, and configured to deliver the selected at least one voltage pulse to the at least one MLC 1S1R structure.
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公开(公告)号：US20210249081A1
公开(公告)日：2021-08-12
申请号：US16785797
申请日：2020-02-10
IPC分类号： G11C16/10 , G11C16/26 , H01L27/11521 , H01L29/788 , H01L29/40 , H01L29/423 , G06N3/08 , G06N3/063
摘要： A method is presented for temperature assisted programming of flash memory for neuromorphic computing. The method includes training a chip in an environment having a first temperature, adjusting the first temperature to a second temperature in the environment, and employing the chip for inference in the second temperature environment. The first temperature is about 125° C. or higher and the second temperature is about 50° C. or lower.
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公开(公告)号：US20210050518A1
公开(公告)日：2021-02-18
申请号：US16538262
申请日：2019-08-12
发明人： Nanbo Gong , Takashi Ando , Guy M. Cohen
IPC分类号： H01L45/00
摘要： Methods and structures for fabricating a semiconductor device that includes a reduced programming current phase change memory (PCM) are provided. The method includes forming a bottom electrode. The method further includes forming a PCM and forming a conductive bridge filament in a dielectric to serve as a heater for the PCM. The method also includes forming a top electrode.
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10.发明授权公开(公告)号：US11948618B2
公开(公告)日：2024-04-02
申请号：US18133867
申请日：2023-04-12
发明人： Nanbo Gong , Takashi Ando
IPC分类号： G11C11/22
CPC分类号： G11C11/2275 , G11C11/2255 , G11C11/2257 , G11C11/2273 , G11C11/2297
摘要： A device includes a non-volatile analog resistive memory cell. The non-volatile analog resistive memory device includes a resistive memory device and a select transistor. The resistive memory device includes a first terminal and a second terminal. The resistive memory device has a tunable conductance. The select transistor is a ferroelectric field-effect transistor (FeFET) device which includes a gate terminal, a source terminal, and a drain terminal. The gate terminal of the FeFET device is connected to a word line. The source terminal of the FeFET device is connected to a source line. The drain terminal of the FeFET device is connected to the first terminal of the resistive memory device. The second terminal of the resistive memory device is connected to a bit line.
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